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Altera_Forum
Honored Contributor I
1,006 Views

de2 webserver template, "full feature".sof error

Hello all, this is my first post after two days searching I cannot find a solution to this sealeslly easy problem 

 

I am trying to run the webserver template in nios II IDE, using the provided full featured hardware design but I get the following error: 

 

 

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 

Pausing target processor: not responding. 

Resetting and trying again: FAILED 

Leaving target processor paused 

 

 

I havent made any modifications to neither the quartus II design file or the Nios II code.  

I am about to go nuts here. 

 

I have been successfull in running other templates such as the hello world template in the same rig I got setup 

 

I appreciate any help thanks 

 

Altera (Terasic) DE2 devel Board 

quartus II and Nios II IDE version 7.2  

Windows XP 64 bit service pack 2.
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8 Replies
Altera_Forum
Honored Contributor I
65 Views

Please you guys, someone here have to have seen this problem somewhere.  

 

Its not like I tried to compile anything, there were supposed to be turn-key applications so we could learn from them but all I get is errors. 

 

I appreciate any help. Its been a couple of months with this new development board but still I haven't been able to do much with it. 

 

Thanks, 

Gabriel
Altera_Forum
Honored Contributor I
65 Views

Did you upload the provided .sof file to the FPGA before uploading the software or did you upload a .sof file you compiled yourself from the full featured project? 

In the latter case, if you don't have the license for the Nios CPU and some other componenst (such as Ethernet) then your design becomes time limited (it goes into a *_time_limited.sof file) and if you close the evaluation window then all the licensed IP (including the Nios processor) will stop working. 

If this isn't the case, the reasons for a Nios CPU not to respond are usually basic, i.e. a bad clock or reset signal. Is there a reset switch on the board that could be stuck?
Altera_Forum
Honored Contributor I
65 Views

 

--- Quote Start ---  

Did you upload the provided .sof file to the FPGA before uploading the software or did you upload a .sof file you compiled yourself from the full featured project? 

In the latter case, if you don't have the license for the Nios CPU and some other componenst (such as Ethernet) then your design becomes time limited (it goes into a *_time_limited.sof file) and if you close the evaluation window then all the licensed IP (including the Nios processor) will stop working. 

If this isn't the case, the reasons for a Nios CPU not to respond are usually basic, i.e. a bad clock or reset signal. Is there a reset switch on the board that could be stuck? 

--- Quote End ---  

 

 

 

The supplied .SOF that was in the example directory inside of the instalation folder of the niosII ide.  

 

IM still pretty green to this enviroment so I just wanted to see something run before I started writing code.  

 

as far as clock, since I did not compile the HDL on quartus (i'm just flasing the .sof) that has't been changed, only if there is a physical switch that Im unaware about.  

 

I did actually try to open the quartus II project file in quartus and cheked on pin assignment that the n_reset line is assigned to pin_c5 which it isn't very clear, but in some research, that pin supposedly is connected to the Audio codec.  

 

Now it seems very weird to me because, I think Altera, or terasic wouldn't make such a mistake in providing that .sof file with such an error, or if they would someone here would have ran into it.  

as it is a very common development boad. the DE2 is .  

 

So Im actually stuck, Now, in the same board I was able to run a different .sof file , provided with the Textbook Im following the it ran fine without a hitch. so... I dont know now.. 

 

 

we actually have two board, and both problems show on both ( we are trying to finish our final project on this board, and it requires two distinct boards) 

 

By the way, I do know about the time limited thing , I had ran into it before, during a tutorial so I know what to do when I see that.
Altera_Forum
Honored Contributor I
65 Views

It may sound stupid but are you sure you are using the correct .sof file? There are several kits that are called DE2. 

As for the pin, yes it is weird. Did you check the pin assignement in the kit documentation? Sometimes the documentation is wrong, only the schematic is a reliable source of information.
Altera_Forum
Honored Contributor I
65 Views

I am as sure that the sof file Im using is for my board as one could possible be without actually coding them.  

 

As I read through the literature from altera, specific to my board, they all tell me to go to the same path I've been using to reach the .sof file. 

 

as far as the pin,  

 

I have attached a little png, a screen cap of the schematics, and if you could kindly take a look at the bank3 top right there i'll notice a pin c5. 

 

Just for my own insecurity , could you please tell me for sure that that pin c5 is the same in pin planner pin_c5. if so than, yeah it looks like the reset is connected to the audio ADC.
Altera_Forum
Honored Contributor I
65 Views

No you are right, it looks like C5 is connected to an ADC clock. 

Do you have any other example design for this kit that you can try?
Altera_Forum
Honored Contributor I
65 Views

Daixiwen. Thansk for the reply.  

 

Sorry fr the late reply. I have been away. 

 

Yes I have used other design examples and they do work but they do not have the peripherals needed to run the example code. 

 

As I was only trying to run turnkey demos provided with the board just to see how stuff works. 

 

But thanks I think that we have confirmed that provided design file is flawed.
Altera_Forum
Honored Contributor I
65 Views

If possible, you should start with one of the design examples that work and add the peripherals you need one after the other. The design you are trying to use may have been written for another version of the kit.

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