Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12453 Discussions

design of look-up table for logic element

Altera_Forum
Honored Contributor II
823 Views

I am working in the area of performing dynamic reconfiguration using soft-core processor.Now i need to design the logic element which is the basic building unit of altera fpga in order to interface with nios-ii processor and for run-time reconfiguration.actually i want to know,how to make logic element and the vhdl code to make logic element as the custom component. plz help me.I didn't got a clear view

0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
94 Views

I dont really get a clear view of your question either. What do you mean by "logic element"? The basic building blocks of FPGAs are LUTs and registers.

Altera_Forum
Honored Contributor II
94 Views

I really need to include the processing element of fpga as my custom component in SOPC builder.

Reply