Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

dtb generation

Altera_Forum
Honored Contributor II
827 Views

Hi community, 

 

I want to modify my devicetreeblob-file. After weeks of searching the web, I now know how to generate this dtb (http://www.rocketboards.org/foswiki/documentation/gsrd141devicetreegenerator). 

But I do not know how to modify it. 

I am trying to bring up two tse-interfaces (http://rocketboards.org/foswiki/projects/alterasoctriplespeedethernetdesignexample). 

I have installed Quartus V14.1 including all addons. 

Linux is built in a virtual machine, running ubuntu 12.04 LTS. 

 

what works: 

Linux is booting and does load the "altera_tse" driver. 

 

what does not work: 

Linux / the driver does not fully recognise the two interfaces. 

On boot up the error-message shows up: altera_tse c0010000.ethernet: resource s1 not defined 

(c0010000 is the base address of my first tse, the same error shows up for the second tse-interface) 

If I list my brought up interfaces with "ip addr", they are not listed. 

 

My questions: 

1. What do I have to write into the xml files, so Linux/ the driver will recognise the tse-interfaces? 

2. If I would add other IP-Cores to the FPGA, where would I get the information about what to add to the xml-files? 

 

Thanks in advance, 

Fabian
0 Kudos
0 Replies
Reply