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My design includes a 1.8V Mobile DDR (which seems to be working fine), a Serial Flash,Micron 256Mbit, UART.
NIOS reset vector: epcs Controller , exception vector: DDR controller, the whole project be working fine with jatg. SOF and ELF file create JIC file, serial flash program OK. Reboot,power up, FPGA configuration be fine. But elf code once in a while be running OK, many times not running. After simplification of Project code ,including 'mem' ,'printf',pointer variable instruction, etc., cause of obvious hindering EPCS running, and many available codes, NIOS be running fine. But elf code once in a while be running OK, many times not running. Maybe, turn off PCB power,turn off PC, disconnect JTAG cable,one Night or hours, the board we design be running OK. Any suggestions? Thanks a lot, AaronLink Copied
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