fast passive parallel configuration using NIOS II

[Altera_Forum]

Hello,  

 I am new to cyclone FPGAs hardware design, I have been given a requirement for a hardware which has 4 Cyclone IV E devices. I already have set up active serial and JTAG configuration provisions.   One of the FPGAs is supposed to have a NIOS II processor. My question is, if I use a CFI NOR flash in my design can I use Fast passive parallel configuration to program the 3 non NIOS FPGAs. FPP documentation says that external microprocessor can be used. Can this processor be NIOS?   Also, if it is possible, is it required to connect the flash directly to configuration data lines of the FPGAs or the data can be loaded in NIOS first and them be routed by it to the other FPGAs?  A side question, if I use a flash for non configuration purposes(just to store some data), can the lines be connected in any fashion, or still I have to follow some rules to connect the data and address lines?

[Altera_Forum]

Yes, you could use your Nios FPGA as the micro to configure the other three non-Nios FPGAs from the CFI FLASH. You'll just have to decide how to boot the Nios FPGA. You won't be able to boot that from the same CFI FLASH without an external controller. 

 You can choose whether to connect the CFI FLASH's data pins directly to the configuration data lines (of the 3 non-Nios FPGAs) or not. Your Nios FPGA will have to control nCE and nCONFIG, and monitor nSTATUS and/or CONF_DONE, but whether you route the data directly from the FLASH or through the Nios FPGA is up to you. Going through gives you greater flexibility, but consumes more pins.  Happy New Year, Alex

[Altera_Forum]

--- Quote Start ---  Yes, you could use your Nios FPGA as the micro to configure the other three non-Nios FPGAs from the CFI FLASH. You'll just have to decide how to boot the Nios FPGA. You won't be able to boot that from the same CFI FLASH without an external controller.  You can choose whether to connect the CFI FLASH's data pins directly to the configuration data lines (of the 3 non-Nios FPGAs) or not. Your Nios FPGA will have to control nCE and nCONFIG, and monitor nSTATUS and/or CONF_DONE, but whether you route the data directly from the FLASH or through the Nios FPGA is up to you. Going through gives you greater flexibility, but consumes more pins.  Happy New Year, Alex  --- Quote End ---     Thanks and Happy new year :)  Just one more side question, I have SDRAM, CFI NOR, NAND flash, SRAMs in my system, is the IP core information required for pin planning and can I connect the pins according to the data lines given in the data sheets? I am not very sure about altera FPGAs, so this is just to be certain.

[Altera_Forum]

You should be relatively free to connect any of those how you like to the general purpose I/O in Cyclone IV (and other families). The 'IP core information', as you put it, isn't necessarily required. However, I would always recommend checking any chosen pinout with Quartus prior to committing to a new PCB. I think you'll have little trouble with any of those memory types. 

 Cheers, Alex

[Altera_Forum]

--- Quote Start ---  You should be relatively free to connect any of those how you like to the general purpose I/O in Cyclone IV (and other families). The 'IP core information', as you put it, isn't necessarily required. However, I would always recommend checking any chosen pinout with Quartus prior to committing to a new PCB. I think you'll have little trouble with any of those memory types.  Cheers, Alex  --- Quote End ---    Thank you very much!