Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++

help creating dtb

Altera_Forum
Honored Contributor II
2,085 Views

I'm trying to create my own Quartus project for a Teraisc DE1-SoC board, and I'm stuck generating the bootloader. My end goal is to create a new SD card image that can boot the board with my own design in the FPGA part of the Cyclone V. 

 

In order to generate the .dts and .dtb files, I need soc_system_board_info.xml and hps_clock_info.xml. I have download versions that are supposed to match the reference design for the DE1-SoC. However, I do not know how these were created, and they won't match my new Qsys project. (The reference design uses IP some cores I don't have have a license for and don't need. I'm using some, but not all, of the HPS peripherals from the reference board.) How do I regenerate these files so that they match my project?
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
1,076 Views

hii!! 

try the function sopc2dts.exe -g and choose file your_project.sopcinfo 

Then, save dts and dtb files! 

ciao
0 Kudos
Altera_Forum
Honored Contributor II
1,076 Views

Hi,  

 

After compiling your kernel, check this directory: /arch/arm/boot/dts copy these three files: 

 

- skeleton.dtsi 

- socfpga.dtsi 

- socfpga_cyclone5.dts 

 

Now from the Embedded Command Shell, compile these files into a single .dtb file: 

 

dtc -I dts -O dtb -o socfpga.dtb socfpga_cyclone5.dts 

 

Copy the generated socfpga.dtb to your SD card and you should be able to boot kernel. 

 

I tried this with kernel version 3.10-ltsi, and I think all kernel versions come with .dts files. 

https://github.com/altera-opensource/linux-socfpga 

 

You can edit the socfpga_cyclone5.dts file and add the entries you need and then compile it again. 

 

Note: you can use the sopc2dts.exe with your .sopcinfo (you get the dts file) to get the dts entries of your FPGA module.
0 Kudos
Reply