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12437 Discussions

hold time violation in qsys system

Altera_Forum
Honored Contributor II
879 Views

hey! 

 

I build a system with Qsys. it incude a nios proccessor and some more ip's from the ip catalog.  

then I generated a qip file and try to compile my project with quartus2.  

after that I noticed that one of the system's components has a hold time violation. 

 

can you please guide me how to solve it? 

0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
124 Views

Check if those paths have different and unrelated source and destination clocks - in most cases they are. If that's the case, add "false path" constraint to ignore those paths. 

 

Thanks, 

Evgeni
Altera_Forum
Honored Contributor II
124 Views

How can I see the path related to the hold time violation?  

I tried in the time quest analyzer's reports, and did not found the path related to my (hold time - fast 110mv -40c model) violation.  

 

Can you please guide me how to find the problematic paths?
Altera_Forum
Honored Contributor II
124 Views

 

--- Quote Start ---  

How can I see the path related to the hold time violation?  

--- Quote End ---  

 

 

In Quartus, open the compilation reports (Processing->Compilation Report). Find the "TimeQuest Timing Analyzer" section (it will be highlighted RED). 

 

Within the TimeQuest section, find the model that is giving you trouble (e.g. Fast 1100mv -40C Model) (it will be highlighted RED). Then click on the "Hold Summary" (it will be highlighted RED). 

 

Then, in the right-most pane of the window, you will see a list of all clocks. Clocks with violations will be highlighted RED. 

Right-click on the clock you are concerned with, and select "Report Timing... (in TimeQuest UI)". This will launch TimeQuest and present you with a dialog box full of options. Don't touch anything and just click "Report Timing" button at the bottom. 

 

When TimeQuest is finished, the display should have a "Summary of Paths" listing. Paths with violations will be highlighted RED. It will show you the path and the source/destination clocks, as OutputLogic mentioned.
Altera_Forum
Honored Contributor II
124 Views

Thank you all for your answers. 

 

I check those paths in the technology map. 

Those paths use different clocks, but they are related!  

 

My main clock goes through an IOBUFF block, and then goes to CLKCTRL block. (Both blocks are automatically instantiated there by quartos and not by me, so I can't see them in the design files). the first node in the path use the main clock right after the IOBUFF block and the last node use the main clock after it pass the IOBUFF block(just like most of the design do). 

 

Is it still o.k.? If not - what can I do to fix this hold time violation?  

I will be also glad if you can aim me to some information about why quartos do it, what is it actually means and so on...
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