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Altera_Forum
Honored Contributor I
1,171 Views

how can i access the output

my custom logic takes 26 clk cycles to produce the output, how can i access the output just it finish processing the inputs.

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7 Replies
Altera_Forum
Honored Contributor I
23 Views

Add 'waitrequest' output to your Avalon-MM interface, and keep it asserted while the processing is in progress. Issue your 'read' immediately after the processing starts and it will be held until the processing completes.

Altera_Forum
Honored Contributor I
23 Views

but my logic is pipelined, and have an input each clk, is ther any function that can use as a timer in c, instead implementing it in vhdl.

Altera_Forum
Honored Contributor I
23 Views

 

--- Quote Start ---  

but my logic is pipelined, and have an input each clk, is ther any function that can use as a timer in c, instead implementing it in vhdl. 

--- Quote End ---  

 

 

You don't need a timer - you're only going to wait 26 clocks. I used a macro that did memory reads to get me the number of clocks to stall before reading: 

 

#define WAIT_CLKS() do { volatile int x, *y = &x; (void) *y; (void) *y; (void) *y; } while(0) 

 

Use a scope to figure out how many reads from *y you need to wait 26 clocks and simply use this macro where you want a write, wait, read sequence. 

 

BillA
Altera_Forum
Honored Contributor I
23 Views

Thanks BillA for your reply; 

but how can I define the 26 clks in this delay loops. 

waiting for your reply. 

Thanks
Altera_Forum
Honored Contributor I
23 Views

As I wrote previously, a scope is the best way to get the right clock pulse. Remember if there is an interrupt during this 26 clocks the delay could be much longer. If this is a problem, you need to protect the delay from interrupt. Maybe you should implement this I/O in hardware since that's well suited for waiting 26 clocks. 

 

BillA
Altera_Forum
Honored Contributor I
23 Views

Did you mean a function like this:  

void wait(int t) 

int i; 

volatile int x, *y = &x; 

 

for (i=1;i<t+1;i++) 

(void) *y; 

}
Altera_Forum
Honored Contributor I
23 Views

If your custom core is accessed rapidly with multiple inputs (and as a result it returns multiple outputs) I don't recommend having software in the critical path. For example if I had some hardware that simply sums all the inputs I write to it and it provides me the running sum as the inputs are arriving I would have one slave port I write the inputs to and a second slave port I read the results from. Results would be written into a buffer (FIFO) so that I could iscolate the input and output and access the component faster. This would also be the most appropriate approach if you used a DMA engine to move data to/from the hardware which is much more efficient than having a processor moving bulk data. 

 

Having the processor twiddling it's thumbs for 26 cycles per input is not very efficient so having a FIFO iscolate the input and the output so that the processor can perform other tasks in between is a more efficient use of those processor cycles. If you don't care about this inefficiency then just implement you component to either issue a wait request when you go to read the result, or just include the read data valid signal so that it can return the valid data any time after the CPU issues the read.
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