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Altera_Forum
Honored Contributor I
1,225 Views

how to embeded the Nios software into FPGA sof file?

Hi, I'm confused about combining the Bios software with the FPGA hardware code. In Nios I generated the mem_init file, and added them into my quartus project, and the reset vector I set to the on-chip ram, then after I programmed the .sof file into FPGA, it works; I generated the .jic file based on the sof file and programmed into EPCS device, but FPGA cannot boot from EPCS device. I changed the reset vector to EPCS controller, it still doesn't work. But if I use Nios command to convert the sof and elf files to hex file and combine the hex files to jic, then it works well. So what's the reason?

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Altera_Forum
Honored Contributor I
73 Views

There are two different ways for NiosII executable code storage: 

 

1. Executable code is stored in On-Chip RAM directly. This is according to your first attempt: 

 

--- Quote Start ---  

In Nios I generated the mem_init file, and added them into my quartus project, and the reset vector I set to the on-chip ram, then after I programmed the .sof file into FPGA, it works 

--- Quote End ---  

 

In this case you need not the epcs_flash_controller in your system. Both Reset and Exeption vectors must point to On-Chip RAM. If you convert this sof file to jic, and program this jic to EPCS, your project will start the work after power is up. 

I don't know, why your project doesn't start. Did you recompile quartus project after mem_init hex file was added? 

If yes, may be your jic has been created incorrectly, or some problem occured during EPCS programming. 

 

2. Executable code is stored in the EPCS. This is according to your second attempt: 

 

--- Quote Start ---  

I changed the reset vector to EPCS controller, it still doesn't work 

--- Quote End ---  

 

In this case the epcs_flash_controller is nesessary in your system. The reset vector must point to the epcs_flash_controller, which contains the bootcopier code. The exeption vector must point to On-Chip RAM because your .text segment is still located there. 

After power is up, NiosII start the execution of the bootcopier code from epcs_flash_controller internal ROM. This bootcopier gets application executible code from EPCS and stores it into On-Chip RAM. After bootcopier has finished its work the control passes to the application executible code in the On-Chip RAM.
Altera_Forum
Honored Contributor I
73 Views

hi, Stewart, thanks! Now I solved the first problem, just re-build the whole Nios project, still select the on-chip RAM, it can work, I don't know why. 

For the second problem, I'm doing another test, I tried to create a jic file in which two sof files are invloved, with either one of the sof files FPGA can works and can boot from EPCS, but FPGA cannot boot from EPCS with the new jic file, I just followed the guidance found in Altera Wiki, it cannot work.
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