.jic file procedure for EPCQ256

[Altera_Forum]

I saw a previous post commenting that the NIOS flash programmer will not work for the EPCQ devices. Given that, what is the procedure creating a .jic file that I can blow into the EPCQ256 for Active Serial x4 configuration? I already have a .sof that brings the NIOS core up, and then I can program it via JTAG. However, I'd like to have the program in the EPCQ so that it starts as soon as the FPGA comes out of reset. Thanks.

[Altera_Forum]

I went back to SOPC Builder which seems to be more reliable than QSYS. 

 My system works; I can program it via JTAG and everything is good.  However, I simply cannot figure out how to get this blown into the configuration device.  I have set the reset vector to the EPCS device. I have the exception vector in on-board RAM.  I have tried the directions here: http://www.altera.com/support/kdb/solutions/rd12092009_471.html  But they didn't seem to work. The FPGA never gets configured (LED's never light that I have tied to come on).  Any suggestions?

[Altera_Forum]

What family is FPGA and what is the configuration device: EPCS or EPCQ ( since You mentioned both ) ?

[Altera_Forum]

The FPGA is Arria V series. The configuration device is an EPCQ. However, the flash controllers only seem to communicate in EPCS/EPCQx1 mode in any of the Nios cores. 

 Nominally, I shouldn't *need* the .jic file. I should be able to use the flash programmer to write the EPCQ device. Unfortunately, that doesn't seem to work either.