jtag programming bug

[Altera_Forum]

Hi all,  

 I'm using DE0-CV board and running Nios II on this board.  (I'm running a custom application on the board which is basically 7 different ''for'' loops. I can find the duration and beginning and end of each loop with looking at the EM signals generated by the FPGA.)   My problem is sometimes when I program the board (using Quartus programmer and usb blaster) the duration of my application may become much more longer (1.5x) than other runs (with exact same inputs and code). In other words, each time I disconnect the USB cable and reconnect it and reprogram the board, the runtime might be either normal or 1.5x slow (but it is the same across each programming interval. i.e. after I program the board, each time that I run the application it takes same amount of time) so it seems like the reason for inconsistency is programming the board.   I was wondering if anybody has seen something like this? I would really appreciate it if somebody can help me figuring out what the problem is.    BTW I'm using Quartus/Eclipse (latest version) on Linux.

[Altera_Forum]

That is very strange. I presume your hardware design is meeting timing based off a .sdc file?

[Altera_Forum]

yes it does.

[Altera_Forum]

I would not attribute this to programming. Programming is kind of binary. It either works or it doesn't. It doesn't program the board differently some times. 

 If possible, I'd add Signaltap to the design to see how it's running in hardware. Maybe you can capture signals when the design is not behaving the way you intend to help figure out why.  Have you simulated this design in, say, ModelSim?

[Altera_Forum]

--- Quote Start ---  I would not attribute this to programming. Programming is kind of binary. It either works or it doesn't. It doesn't program the board differently some times.  If possible, I'd add Signaltap to the design to see how it's running in hardware. Maybe you can capture signals when the design is not behaving the way you intend to help figure out why.  Have you simulated this design in, say, ModelSim?  --- Quote End ---    No I haven't simulated the design there. the reason that I think it's because of the programming is that I'm literally running the exact same design on a board without changing any file, input, etc.

[Altera_Forum]

Yes, but even if everything is the same, that means the programming is the same as well. What are you using to calculate the time for your application? I presume you're using alarm functions.