On a DE0 Nano Soc I am trying to setup a DMA from a FIFOed Avalon UART IP, to the DDR3 memory of the HPS, under control of a NIOS processor.
The UART is a Memory-mapped Avalon Slave, and the data it receives is available by reading one specific base address. The UART has an embedded FIFO, so each read operation to this address returns the next value in the FIFO.
When I read the UART FIFO address "manually" from the NIOS program, no problem, I retrieve the characters successfully.
Then I tried to build an extended DMA descriptor instructing the mSGDMA to perform a transfer with the UART FIFO address as the source address, some address in DDR as the destination address, and with a read stride of 0, such that consecutive reads that the DMA performs are always at the same address (i.e. the UART FIFO reading address, effectively emptying the FIFO as it goes).
Somehow this fails to read the UART FIFO data, after the DMA I check the UART FIFO level and it is still the same.
My code boils down to this:
(void*)FIFOED_AVALON_UART_2_BASE, /* read address */
frameLength , /* size in bytes of data*/
0, /* sequence_number */
0, /* read_burst_count */
0, /* write_burst_count */
What am I doing wrong ? It is not shown above but of course I check the return codes from these two calls and they are OK.
What is a good way to investigate what the mSGDMA actually does and why it fails ?)
Thanks for contacting Intel PSG Forum.
Have you seen this video?
I gave a description on how to run mSGFMA and stream data from a source to a memory.
I did the mSGDMA to HPS DDR before. The first step I confirmed is, the data flow is correct (from source to on chip memory). Then, I changed the destination to HPS DDR. Please note that you would not be able to access HPS DDR until Linux is booting.
have you used the prefetcher mode?
I checked the video, but this is an example of Avalon-ST to Avalon-MM transfer.
In my case I need an Avalon-MM to Avalon-MM transfer.
I first tested it with a transfer from OnChip memory to DDR, with the default stride of 1 word increment at each transfer, and it works fine (and yes I have Linux running on the HPS side and initializing the DDR)
It is only when I changed the source in the descriptor to the base address of the UART IP, and adjust the read stride to 0 (so that successive transfers always read the same input adress), that things apparently don't work anymore, somehow the read transactions on the Avalon bus are not performed because the UART FIFO level does not change after the DMA operation.
About the prefetcher: no I have not yet used this option. Can you please explain how it could be relevant to my problem ? I see it as a performance optmisation option only?
The concept should be the same, we have used ST to MM in the video since the source of the pattern generator was ST, and to simplify the design we used ST to MM.
Prefetcher mode enables the external descriptor master connection.This means the descriptors location will be outside the mSGDMA. With the prefetcher enabled, it will complicate the mSGDMA flow.
Are you using the UART RS-232 Serial Port intel FPGA IP ?
once I know from you which UART IP, I will do a quick test.
I am using the "FIFOed Avalon UART IP" from here:
( I am using the latest version)
When I read the UART FIFO using NIOS code (i.e. using IORD_FIFOED_AVALON_UART_RXDATA macro that wraps an "ldwio" NIOS instruction to access the FIFO base address to pop the FIFO), it works fine. I assumed that it would be fine for the mSGDMA to be doing the read access at this FIFO base address, but there must be something different between what the ldwio instruction does and what the DMA read access does.
from this conversation. can someone help me in writing a c code for msgdma prefetcher enabled. with great difficulty i am able to do MM-to-MM transfers from ddr4 to custom memory block via mSGDMA IP block. but now i want to do with prefetcher enabled in it which i think it will save more cycles. plz i dont want videos/reference HAL driver pdf's. i had a look on all those. Thanks