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Valued Contributor III
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mSGDMA transfer from DDR3 using FPGA2HPS-SDRAM interface

Hi, 

 

I am using a DE1-SoC board equipped with Cyclone V SoC, I have a custom circuit on FPGA with Avalon interface, I want to transfer some data from the DDR3 (of the HPS) to this circuit. I used an mSGDMA to do that. I am using linux and I began with a false driver so I control all of this from the user space using mmap() function.  

 

In Qsys I activated the the F2S interfaces, I connected the read port of the mSGDMA to this interface (avalon than AXI), and the write port to my circuit. both of the ports are 32 bits data wide. 

I have mmaped a region on SDRAM to write directly to it the source data, I mmaped the csr and descriptor reg too. the preloader and all headers file are updated according to the design. 

The Linux stuck when the transfer begin. 

I have used SignalTapII to find the problem. 

first observation is the transfer begin, it transfers the eight beats of addresses then it reads one beat of data and it stuck. 

second when I am using avalon on the F2S interface: 

the address demanded by the mSGDMA (which is the same as my c program) is divided by 8 in the input of the F2S interface, which is not the problem when I choose an AXI interface. 

 

I would like to know where is the problem, is there any one who face this problem yet. 

If It is possible, is there any tutorial that shows the procedure to read data from F2S interface 

Thanks
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Valued Contributor III
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Have you already tried this tutorial: 

 

https://rocketboards.org/foswiki/projects/datamover 

 

I will have to do this quite soon, but have not done it, so I would be happy to learn with you.
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Valued Contributor III
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--- Quote Start ---  

Have you already tried this tutorial: 

 

https://rocketboards.org/foswiki/projects/datamover 

 

I will have to do this quite soon, but have not done it, so I would be happy to learn with you. 

--- Quote End ---  

 

 

Thanks, I will be too. 

This project use the F2H port instead of this F2SDRAM port, any way I will try it, and see if it is a good alternative.
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Valued Contributor III
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Hello slh47  

 

Is your design working? 

Can you please guide me in how to write a driver in C for mSGDMA running on Linux at HPS. 

I don't know from where to start...anything would help. Maybe some code to start with would help. 

 

I have done the FPGA design with the mSGDMA connected to F2H_Sdram. 

 

I would really appreciate any help.
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Beginner
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Hi,

I am trying to implement triple speed ethernet in nios processor using modular scatter gather dma (msgdma) controller. I have build the qsys. For memory i have used ram. I have called 2 msgdma one for receiving in streaming to memory mode and one for transmitting in memory to streaming mode. I have done the interconnections in qsys platform and generated the HDL successfully. The sopcinfo file is also generated. Using this sopcinfo file i tried to generate the bsp. The bsp generates but when i try to build the bsp project in eclipse the build fails. It says that " fatal error. altera_msgdma.h. No such file exists."

I am using Quartus 18.1. I cannot downgrade to lower version as i have progressed a lot in 18.1 and now cannot migrate to a lower version because of dependency issues.

Actually this file is missing in alt_avalon_tse.h. The altera_msgdma.h exists in the installation folder of quartus 18.1 in c drive. But some how when i try to build the bsp it doesn't pick that file and throws the above mentioned error. I have tried to manually move altera_msgdma.h and altera_msgdma.c file into the incude and source file of the driver folder of the project file. After doing this the bsp builds, but the actual project build fails.

I am not using linux

Kindly guide

 

Regards

Av

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