Honored Contributor II
03-18-2014 04:47 PM
Hi,I recently asked a question about the mSGDMA on this forum here (http://www.alteraforum.com/forum/showthread.php?t=44113&p=183258#post183258). But I'm starting a new thread as I think the issue I'm currently having is unrelated. I am using the mSGDMA in ST->MM mode to save data from an avalon stream to DDR3 memory. My write to DDR3 works perfectly for the number of words that fit in the write master FIFO. Once the FIFO has been filled, all subsequent writes to the DDR3 have skipped an equal number of words from the stream. I have signal tapped the relevant stream to see what is happening. It seems the data ready signal of the avalon stream is only being asserted for one clock before being deasserted for twelve clocks. During this time I assumed the data should be getting put into the write master FIFO however the data in these twelve clocks is being lost. Should the data ready signal for the input stream be asserted as long as there is room in the write master FIFO? If so, is there an obvious reason why my FIFO might not be getting emptied and ready is being deasserted? Reducing the size of the write master FIFO makes the errors begin earlier so it is not a coincidence that the errors occur at the end of the FIFO length. Thanks for any help.