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Altera_Forum
Honored Contributor I
813 Views

master_waitrequest

Hi everybody, 

 

I have a problem in my nios II simulation. I have used the avalon memory-mapped master template for writting into a sdram memory. When I simulate the component and the master_write signal is asserted, the master_waitrequest signal reminds in a high level for 143350 ns, which is too long time.... 

 

I have upload the sdram parameters.  

 

Anyone can help me to solve this problem? 

 

Many thanks.
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3 Replies
Altera_Forum
Honored Contributor I
54 Views

OK I will try to answer myself, until 200000ns the sdram is not initialized by nios. After this time the waitrequest signal is reduced to 143ns.

Altera_Forum
Honored Contributor I
54 Views

Is that the first/only cycle, part of a back to back sequence, or a single cycle separated by a lot of idle time? 

It might be that the initialisation hasn't finished. 

My experiments with SDAM seemed to imply that, under normal circumstances, the avalon cycle for isolated writes terminated immediately. My suspicions are that writes to adjacent addresses are buffered so that they can be sent as a burst.
Altera_Forum
Honored Contributor I
54 Views

That memory controller is not initialized/calibrated by Nios II, that is the old SDR SDRAM controller. Just like the newer DDR SDRAM controllers there is some time spend while the controller is coming up out of reset where it can't perform data accesses off-chip and as a result wait request must be asserted. I can't remember how long that delay is but 143us sounds about right.

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