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Valued Contributor III
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missing vertical sync signal on clocked video output Core

The video IP core I am working on is working. 

 

But there is one problem, the output vertical sync signal is missing from clocked video output Core. 

 

Please help me to find what is the reason of this missing output vertical sync signal. 

 

Many thanks. 

 

David.
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Valued Contributor III
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aa.. ok i may be giving dumb question but, as i get it you are working on video image , which should give you vertical synchronization signal at a given moment, and the signal is not there? if im correct, please tell us what video format are you using? (pal,secam,ntsc)

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Valued Contributor III
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The input video is in customed format which is 1220 active pixels per line + 60 inactive pixels, and 876 active lines + 24 inactive lines. 

 

I plan to convert above customed video to SVGA, but VSYNC is missing from converted output video. 

 

Please let me know any suggestions. 

 

many Thanks.
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Valued Contributor III
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Any answers from Altera staff?

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Valued Contributor III
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Maybe I better switch to Xilinx FPGA.

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Valued Contributor III
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If you don't get any answer from the forum, it probably means that no one else ran into that problem before or has an idea about what the problem could be. If you want official support or answer from Altera you should use mySupport or contact your FAE. On this forum you'll see mostly Altera users.

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Valued Contributor III
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all i can do is help you to solve the problem step by step by using knowledge that iv got. are you using your own written module? or is the converter module some quartus megafunction or something? in any case, check your VGA's "G" wire. there are 3 analog signal wires R,G,B. in most cases the signal architecture is such that the Vsync is mounted into the G wire. put an oscilloscope probe there and check if the signal is present, once in every 64 microseconds you should see it. if its there, this means altera processor recieves the signal but fails to decode it. there is one more thing, if the vsync is provided seperately,by the device from which you recieve the image, then put a probe on it, check if there is anything inside there. if there is a Vsync signal, and your quartus module fails to read it, you should analyze the entire frame signal and generate your own Vsync from it. iv done it; i had clean pal signal, with Vsync embeded in it. so i captured the vsync region and generated my own vsync impulse from it. in short it is possible. but i havent recieved vga format so i do not know how exactly your vsync looks. if you could tell me a standart name for your format (like "IEEE some number" or "ITU some number", if i remember correctly, company VESA was developing VGA standarts...) that could help us to search the signal's architecture and find out how the vsync is provided. 

look, http://www.leadsdirect.co.uk/technical/svgawiring.html here the connector provides vsync impulse by seperated pin (N14).maybe you should try to capture it in the register and write a code to recombine it with the image you get after convertion. 

 

if you want it this way, lets go through it step by step. thats all i can do.
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Valued Contributor III
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In the Qsys component editor, there is an option for the sync signals. "Embedded in video" or "On separate wires". You need to select "On separate wires". 

 

See page 11-4 of ug_vip.pdf
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Valued Contributor III
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Anyone have solved the missing Vsync from the CVO issue? I have run into the same problem with a simple Test Pattern Gen -> Clocked Video Output setup. Hsync and RGB signals operate normally but Vsync output is always flat (logic 0) from the CVO.

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