multi Nios connect to One Pcie

[Altera_Forum]

Hi, 

 I'm trying to connect an array of Nios processors that are designed by Qsys to ONE Pcie (CycloneIV pcie ip compiler-completer only) module that is designed by SOPC.  I'm going to send data from PC to these Nios processors and read some data from them. I think that i should use a share memory between these processors. but i don't know how to do it clearly?  some points: 1- i don't want to use DMA. 2- every Nios processor should be seperate Qsys design.  Both of Nios and Pcie have Avalon master port. how should i connect these processors to pcie.  Does anyone have any suggestion?

[Altera_Forum]

Instantiate the core using Megawizard and don't add it to any of the Qsys systems.

[Altera_Forum]

thanks for your reply. 

 But I know how to instansiate these seperate nios processors. I'm looking forward to the BEST way of connecting the pcie core and these nios processors.

[Altera_Forum]

Think twice if You really need so much processors? 

 If yes, then I'd offer You to check Qsys capabilities of using subdesigns.

[Altera_Forum]

Using a shared memory between several SOPC/QSYS seems extremely complicated for me. You'd need to write custom components that implement Avalon masters and slaves and open a communication between the different systems, but you would have to do yourself all the memory mapping if you indend to share more than a memory, and possibly have to cope with different addresses on each CPU... I think it is far easier to put everything in a single QSys design, using subdesigns for each CPU as Socrates suggests. 

 What is the reason why you want separate designs for each Nios processor?

[Altera_Forum]

Memory addressing for each subdesign would be a bit hard task, since all addresses will have to be assigned by hand (currently doing the same on SOPC with >14 memory masters sharing one memory chip).

[Altera_Forum]

Thanks for your replies. 

 After your advices, I redesign my system and I'm going to implement it in a single Qsys design and each cpu as a subdesign.  Is there any thing that i should care if i use one share memory for more than one cpu? (read while write and rtc.)  Is there any need to use some things like hardware mutex?   All my writes and reads to share memory, are done with IORD_32DIRECT and IOWR_32DIRECT. And i thinks these are atomic operation. Am i wright?  Does Avalon interface control these operations or I should use DMA? Thanks.

[Altera_Forum]

Single word read/writes are atomic. 

The Avalon switch fabric will arbitrate the cycles for you. Remember it is a slave arbited bus - ie there is arbitration for every slave, not every master. This means that different masters can access different slaves concurrently.  If you have a lot of slaves that aren't used much, then put them behind a bridge to you only have one large slave arbiter (for the bridge), not one on each slave.  For synchonisation you probably need to use Dekker's algorithm since the the avalon bus doesn't support RMW cycles. Although you could add an Avalon slave that implemented mutexes. Read: return value, set to 1 Write: set to 0 should do it??

[Altera_Forum]

--- Quote Start ---  Thanks for your replies.  After your advices, I redesign my system and I'm going to implement it in a single Qsys design and each cpu as a subdesign.  Is there any thing that i should care if i use one share memory for more than one cpu? (read while write and rtc.)  Is there any need to use some things like hardware mutex?   All my writes and reads to share memory, are done with IORD_32DIRECT and IOWR_32DIRECT. And i thinks these are atomic operation. Am i wright?  Does Avalon interface control these operations or I should use DMA? Thanks.  --- Quote End ---   Although it is designed without the multex in Quartus successfully,does it works well in "Hello world"programe in the Nios IDE ?Does it can work in ucOS or ucLinux? Thank you for reply! Kinder Regards!