multicycle custom instruction not working

Altera_Forum · ‎11-30-2011

Hi All,

I am trying a 3 cycle (fixed) multi cycle instruction module with nios2.

below s my interface.

port (

clk : in std_logic := '0';

reset : in std_logic := '0';

clk_en : in std_logic := '0';

start : in std_logic := '0';

dataa : in std_logic_vector(31 downto 0) := (others => '0');

datab : in std_logic_vector(31 downto 0) := (others => '0');

result : out std_logic_vector(31 downto 0)

);

here 'start' signal is never becoming '1' during my custom call. Also my module s getting only single cycle.

if clk_en = '1' then

if start ='1' then

count <= 10;

reg_out <= "0000010101001111";

elsif count = 1 then

reg_out <= "1100110101001111";

count <= 0;

else

reg_out <= reg_out;

count <= count+1;

end if;

here my reg_out always coming 0

count is also coming 0 always.

(NOTE: from software side the instruction is going correctly as per (ug_nios2_custom_instruction.pdf) -- ie opcode is 0x32 N value s all 0s,

a,b,c reg values are set proeprly.

Also in sopc builder the added custom instruction is shwing its a 3 cycle fixed multicycle instruction.)

Please help.

Also i cud make combinatorial module work proeprly.

Please help soon.

Thanks,

Preethi

Altera_Forum · ‎11-30-2011

I'm no vhdl expert! but aren't you missing a test for the edge of 'clk' ?

Altera_Forum · ‎05-05-2013

I have the same problem. Same logic works when i implemented it as combinational, but since it has limitations i have to use multicycle custom instructions, however I couldn't get the correct result after running the project. In the Quartus ii timing simulation it shows the correct result after 4 cycles.

Thanks in advance for any support that you could provide.

Altera_Forum · ‎07-18-2013

Custom instruction Variable Cycles have 2 port: start; done. you don't have "done"