Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12603 Discussions

need help about flash address!

Altera_Forum
Honored Contributor II
1,873 Views

I have a problem about flash address.I had finished running the uClinux on the stratix develop board(NiosII).But I don&#39;t know that the data (eg. vmlinux.bin)was programed to which address when I "upload" it in the IDE?I want to know how I can program my data to the pointed place?Could you help me? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif

0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
312 Views

I&#39;m not exactly sure what you&#39;re asking for but let me take a stab at it anyways. 

 

The vmlinux.bin file is always uploaded to the beginning of whichever upload target you specify and we "reserve" 2 MB at the beginning of the upload target&#39;s memory space for the kernel. 

 

Your next question regarding "program the data to the pointed place".... I&#39;m not quite sure what you want to accomplish. Can you rephrase the question? It&#39;ll make it easier for us to help you.
0 Kudos
Altera_Forum
Honored Contributor II
312 Views

I know the vmlinux.bin is uploaded to the 0ffset 0x0 of the flash.My question is that other datas are placed to what place of the flash.For example,I want place my own user data to offset 0x0050000,what I can do?(I had creat a image location of offset 0x0050000 in the "board system setting" of the SOPC Builder).The other question is the linux filesystem(ramdisk) is uploaded to what offset? 

I think maybe there is a configration file to resolve those problem.Could you help me?
0 Kudos
Altera_Forum
Honored Contributor II
312 Views

Sorry for the late reply, I&#39;ve been on vacation for the past week... The flash configuration that we use is: 

 

0x000000 kernel image 

0x200000 root filesystem 

 

A minimal root filesystem uses under 2MB of space, so theoretically, you could start placing your memory image at 0x400000. 

 

On Altera based dev boards, I believe that the last 2MB are used to store soft cores for the CPLD. Unless you are using a Stratix Pro in which case the last 4MB are used to store soft cores for the CPLD. 

 

So, in your situation, it sounds like it should be okay provided that the image you are uploading at 0x500000 doesn&#39;t exceed 1MB in size. 

 

I hope it helps...
0 Kudos
Reply