nios II processor not responding after high performance sdram controller addition

[Altera_Forum]

Hi all! 

I'm using the nios II v9.1 in my work and run my projects on the Cyclone III evalution board. It's allright if I use any design without sdram. But every time I add a high performance sdram conroller and try to run any project in the nios IDE, I get the following: "Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused"  I've really tried everything that may cause the error like that but it makes no diffference. I have no idea about it.:confused: Need your suggestions. Had anyone the problem like that?

[Altera_Forum]

Hello, 

 I once had problems with a DE2 Board and Sdram, cause you have to manipulate the clock phase there to get it working, but that will beside that throw a verification error I think. On the Cycl.III Board I had no problems using the ram, but you need a Clock-Crossing Bridge between CPU and DDR to get it going with high performance. Perhaps you will have to leave the programmer open, while using the big Nios to keep the core running.  Have you tried besides adding the component to your design running one of the design examples from Altera with SDRAM included? Perhaps try that out, they have even a memory test application with the evaluation kit sources.  In worst case your core is perhaps not running correctly on the Board. Check for errors again while compiling and check also, if you are downloading the right file.  Good luck!

[Altera_Forum]

The most usual cause for the message you are receiving is stuck clock or reset to the SoPC system. Additionally, I believe if the altmemphy instance is not able to initialize the DRAM properly, I believe it will keep it's reset to the system asserted permanently. 

 Jake

[Altera_Forum]

Why system is not able to initialize the SDRAM? What may cause the wrong initialization? 

Might the high/low clock frequency cause it?

[Altera_Forum]

Hi Kurbanov, 

 I dont know if you found the solution, but I got the same problem and I solved it. The solution is changing the name of the pin assingments.  ARCHITECTURE Structure OF teste1 IS COMPONENT nios_system PORT ( clk_0 : IN STD_LOGIC; reset_n : IN STD_LOGIC; out_port_from_the_LEDs : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); in_port_to_the_Switches : IN STD_LOGIC_VECTOR (7 DOWNTO 0) );  END COMPONENT; BEGIN -- Instantiate the Nios II system entity generated by the SOPC Builder NiosII: nios_system PORT MAP (iCLK_50, iKEY(0), oLEDG, iSW);   The file DE2_70_pin_assignments has assingnmented in a diferent way of the altera example, they use CLOCK_50 that is different of iCLK_50 and others...  I hope it is usefull.

[Altera_Forum]

Hello Renato, 

  I have this problem and I can't find a way to solve it...I have a clock module on Qsys and then the ouput of that is connected to the reference clock....I am not sure what assignments i need to change...I would really appreciate your help.  Renato

[Altera_Forum]

Hi rennyosu, 

 If I understood your question, you have an SDRAM on your system using the General Clock.  If that's the case, depending on the frequency used, the SDRAM input clock has to be phase shifted so you can get the right timing for read/write operations. In this case, the use of a PLL is required.  These two links should help you. http://www.alterawiki.com/wiki/off-chip_memory_pll_tuning_example http://www.alteraforum.com/forum/showthread.php?t=18949  Hope it helps! Renato    --- Quote Start ---  Hello Renato,   I have this problem and I can't find a way to solve it...I have a clock module on Qsys and then the ouput of that is connected to the reference clock....I am not sure what assignments i need to change...I would really appreciate your help.  Renato  --- Quote End ---