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Altera_Forum
Honored Contributor I
883 Views

nios address problem

hi everyone! 

i am new to altra and nios II, recently i am trying to study altra fpga and nios II, i meet one serious problem and i need some help 

i add 3 my ip in the Qsys, seg7(to drive the LED Segment Displays), my_adc(to drive the ADC),my_dac(to drive the DAC) 

i build a project to test my_adc and my_dac in nios II.(the .v files work correct, i have tested them in quartus) 

this is my code: 

# include "alt_types.h"# include "altera_avalon_pio_regs.h"# include "sys/alt_irq.h"# include "system.h"# include <stdio.h># include <unistd.h> 

 

 

void delay(alt_u32 cnt); 

 

 

//&#20027;&#20989;&#25968; 

int main() 

alt_u16 ad_dis; 

alt_u8 cnt = 0; 

 

 

while(1) 

IOWR_8DIRECT(MY_DAC_BASE,0,cnt); 

printf("Write Analog Value = %d,",cnt); 

delay(60000); //&#24310;&#26102; 

ad_dis = IORD_8DIRECT(MY_ADC_BASE,0); // 

printf("Read Analog Value = %d\n",ad_dis); 

cnt++; 

return 0; 

 

 

//&#24310;&#26102;&#20989;&#25968;&#65288;&#24310;&#26102;&#26102;&#38388;&#20026;(2+2*i)us&#65289; 

void delay(alt_u32 cnt) 

alt_u32 i =0; 

while(i < cnt) 

i++; 

 

 

then i download the sof and elf file to the pcb, then the LED Segment start shining!  

then i check the address map 

https://www.alteraforum.com/forum/attachment.php?attachmentid=9349  

and i found that the address of the seg7 is 0x11050~0x11051 

the address of the my_adc is 0x11053~0x11053 

the address of the my_dac is 0x11052~0x11052 

so the reason of the LED Segment shining maybe i write to my_dac (0x11052) but the nios II write to seg7 (0x11050~0x11051) 

why this happen?
0 Kudos
7 Replies
Altera_Forum
Honored Contributor I
37 Views

Hi, 

 

Are you sure the BSP is updated with the correct addresses? Check system.h for MY_DAC_BASE
Altera_Forum
Honored Contributor I
37 Views

While it uses byte addressing, Nios master is 32bit wide and will access MM slaves with 32bit R/W. 

Then your base addresses must be aligned to multiple of 4, otherwise overlaps or data misalignment occur. 

Change base addresses to 0x11050 , 0x11054 and 0x11058
Altera_Forum
Honored Contributor I
37 Views

hi, ngoodger (http://www.alteraforum.com/forum/member.php?u=93169)  

http://www.alteraforum.com/forum/images/statusicon/user-offline.png ,thanks for the help! 

i am sure, i check the system.h file,  

address of the seg7 is 0x11050~0x11051 

the address of the my_adc is 0x11053~0x11053 

the address of the my_dac is 0x11052~0x11052" 

 

these message is found in the system.h file
Altera_Forum
Honored Contributor I
37 Views

 

--- Quote Start ---  

While it uses byte addressing, Nios master is 32bit wide and will access MM slaves with 32bit R/W. 

Then your base addresses must be aligned to multiple of 4, otherwise overlaps or data misalignment occur. 

Change base addresses to 0x11050 , 0x11054 and 0x11058 

--- Quote End ---  

 

 

hi, thanks for the help! 

i think that is the reason! 

but when i use "system=>Assign Base Address", why the Qsys did not recongnize the width of the bus?  

why the Qsys did not assign the adress correctly?
Altera_Forum
Honored Contributor I
37 Views

 

--- Quote Start ---  

While it uses byte addressing, Nios master is 32bit wide and will access MM slaves with 32bit R/W. 

Then your base addresses must be aligned to multiple of 4, otherwise overlaps or data misalignment occur. 

Change base addresses to 0x11050 , 0x11054 and 0x11058 

--- Quote End ---  

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=9377&stc=1  

in the component editor(right click the ip=>edit ),i change the "explicit address span"from 0 to 4,then return the Qsys and click file=>refresh system, then system=> assign base address, then the address changes, the end address minus the base address is 3(correspond to 32bit) 

then i redo the project, the problem solved! 

 

i have another question: 

how to build a ip with several address? 

like i visit base address, return value of reg1; 

i visit base address + 0x04, return value of reg2? 

i remember EDK of xilinx have the add custom ip wizard, in the wizard you can choose how many registers you want to use,and the wizard automatically generate the interface and the procotol of the bus of the microblaze. dose Qsys has the same function? 

 

thanks again for the help!
Altera_Forum
Honored Contributor I
37 Views

 

--- Quote Start ---  

While it uses byte addressing, Nios master is 32bit wide and will access MM slaves with 32bit R/W. 

Then your base addresses must be aligned to multiple of 4, otherwise overlaps or data misalignment occur. 

Change base addresses to 0x11050 , 0x11054 and 0x11058 

--- Quote End ---  

 

 

in the component editor(right click the ip=>edit ),i change the "Explicit address span"from 0 to 4,then return the Qsys and click file=>refresh system, then system=> assign base address, then the address changes, the end address minus the base address is 3(correspond to 32bit) 

then i redo the project, the problem solved! 

 

i have another question: 

how to build a ip with several address? 

like i visit base address, return value of reg1; 

i visit base address + 0x04, return value of reg2? 

i remember EDK of xilinx have the add custom ip wizard, in the wizard you can choose how many registers you want to use,and the wizard automatically generate the interface and the procotol of the bus of the microblaze. dose Qsys has the same function? 

 

thanks again for the help!
Altera_Forum
Honored Contributor I
37 Views

I don't know if Altera provides a custom ip wizard like Xilinx's one. 

Anyway, you can refer to this template to build a full-featured MM slave component: 

http://www.altera.com/support/examples/nios2/exm-avalon-memory-slave.html
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