I have a pretty simple system working with /e cpu . The fpga is on a Terasic DE0 board. I'm using the external SDRAM. When I try to move to /f it will download and verify but then never reach my main().
I've tried the /s also, same issue.
Q: I don't need a license do I for this dev work? I know I need a license for the /s /f options to use without jtag ( in production ) but I think I can dev with the /s and /f right?
I've seen lots of folks talk about disable to cache but I don't think I can right with ext SDRAM?
When I move to /f I have done clean/rebuild everything.... reprogram to ensure there is not state stuff hanging around......
I'm stuck! :-)