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Altera_Forum
Honored Contributor I
788 Views

nios with custom fpga logic

Hello everybody. I am trying to set up a simple example where I implement a simple XOR gate in fpga logic. Then in C code written for the NIOS processor, I will pass several numbers to be XOR'd, and read back the outputs. 

I am following this example: https://www.youtube.com/watch?v=moc3erbiugy&t=75s

My example would appear to be working, except I read back 0 with the IORD command every time. I write to the base address for my XOR gate (0 offset), and read back from that same address in the next line of main.cpp. Am I reading the XOR result from the correct memory address (i.e. same as write address)? Is there an error in how I pass the numbers to the 2 adder inputs? 

 

I am attaching screenshots of:  

1. main.cpp (NIOS) 

2. 2 modules I use to implement a simple XOR gate. 

3. screenshot of QSYS set-up. 

 

I appreciate any ideas thoughts on this. I am puzzled. There are no error messages in the NIOS console/eclipse. 

 

Thanks, 

Matt
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2 Replies
Altera_Forum
Honored Contributor I
40 Views

Hi @moverlin  

 

for some reason I can not get to see your screen shots, can you try to re-post them?
Altera_Forum
Honored Contributor I
40 Views

What is the read latency of your slave interface avalon interface? Seems like your hdl avm_read has latency of 1 cycle. Must set it accordingly in the qsys component.

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