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12455 Discussions

nios2 + 8GB DDR3 /DDR3 SDRAM Controller with UniPHY

Altera_Forum
Honored Contributor II
1,277 Views

I'm trying to finish a simple test with a nios2/f + 1Mb on-chip memory + DDR3 controller.  

The DDR3 controller is connected to 8Gb DDR3 controller, which I took straight from the board manufacturer's reference/test design and works great. 

However (understandably) when you add a NIOS processor it complains with "Address width above 32 bits are not supported for NIOSII) since the NIOS will not use anything above 4Gb. 

Question# 1 - how do I chop down the DDR in such way that QSYS is happy with it?  

Question# 2 - how I can "share" this memory among several processors, ie make it behave as if it was 4x2GB pieces? 

Thank you
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7 Replies
Altera_Forum
Honored Contributor II
140 Views

You can try to use Address Span Extender to configure the 2GB window for each Nios.

Altera_Forum
Honored Contributor II
140 Views

Hi Mike,  

Thank you. I think that's exactly what is needed.  

However when I add all those to the *same* qsys project, it still complains about the address range. I believe qsys uses the biggest address range as a parameter so therefore I will have to break this down into two or more qsys projects. 

Is making the NIOS a subsystem of the main project a solution? Is there any way to accomplish this inside qsys without having to rewire everything through verilog/top?
Altera_Forum
Honored Contributor II
140 Views

I have mocked up and attached a Qsys design. Hope it works. Ignore the errors. :)

Altera_Forum
Honored Contributor II
140 Views

As far as I am concerned, you might marry my sister now brother, thank you!

Altera_Forum
Honored Contributor II
140 Views

You see, after some haggling to erase the other errors, the remaining are one for each NIOS: "Address width above 32 bits are not supported for Nios II".  

So QSYS with NIOS is limited to 32 bit addressing internally no matter what.  

I tried building a subsystem but it seems QSYS does not treat subsystems any differently, it's just a visual aid.  

What I ended up doing is to write them out as two separate qsys blocks and then join them through a pipeline bridge through verilog/top.  

Let's see if it works!
Altera_Forum
Honored Contributor II
140 Views

That does not make sense. Did you make sure that the address span extender slave word address width always is 29 bits or lesser?

Altera_Forum
Honored Contributor II
140 Views

Yes I did. I think the reason is because the NIOS ends up having a 32+ bit base address and qsys does not like it, even though NIOS itself wont use it. 

I did that breakdown and encapsulated the 8GB memory into one qsys project and then created 8 x 1 Gb extenders with manual offsets, which were then exported for happy nioses to digest.  

These were then joined through verilog/top. See attachments... 

It seems to work...
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