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Altera_Forum
Honored Contributor I
887 Views

nios2-mmu linux stuck on #Switching to clocksource timer#?

hello, 

With socrates (http://www.alteraforum.com/forum/member.php?u=7474)'s tips, I soved the memory problem, but it still stuck, see the result: 

Linux version 3.1.0-rc4-01162-g45c9dd8-dirty (liunx@gentoo) (gcc version 4.1.2)# 42 Sat Oct 8 23:37:44 CST 2011 bootconsole enabled early_console initialized at 0xe2004000 On node 0 totalpages: 2047 free_area_init_node: node 0, pgdat d032e198, node_mem_map d03488a0 DMA zone: 16 pages used for memmap DMA zone: 0 pages reserved DMA zone: 2031 pages, LIFO batch:0 pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 pcpu-alloc: 0 Built 1 zonelists in Zone order, mobility grouping off. Total pages: 2031 Kernel command line: bootargs="debug console=ttyAL0,115200" PID hash table entries: 32 (order: -5, 128 bytes) Dentry cache hash table entries: 1024 (order: 0, 4096 bytes) Inode-cache hash table entries: 1024 (order: 0, 4096 bytes) Memory available: 4716k/3353k RAM (1025k kernel code, 2327k data) NR_IRQS:32 Calibrating delay loop... 23.64 BogoMIPS (lpj=47296) pid_max: default: 4096 minimum: 301 Mount-cache hash table entries: 512 bio: create slab <bio-0> at 0 Switching to clocksource timer  

No any response again:cry:, I am puzzled with that, here are(see the attachments) my sopc dts, and linux configuration,thanks for your tips!
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9 Replies
Altera_Forum
Honored Contributor I
78 Views

Did You set the system timer to have IRQ 0? It's a requirement.

Altera_Forum
Honored Contributor I
78 Views

 

--- Quote Start ---  

Did You set the system timer to have IRQ 0? It's a requirement. 

--- Quote End ---  

 

Yes, I try to set it, but it stuck more ealy,see the result: 

cc version 4.1.2)# 51 Sun Oct 9 22:31:39 CST 2011 bootconsole enabled early_console initialized at 0xe2004000 On node 0 totalpages: 2048 free_area_init_node: node 0, pgdat d0334390, node_mem_map d034e8a0 DMA zone: 16 pages used for memmap DMA zone: 0 pages reserved DMA zone: 2032 pages, LIFO batch:0 pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 pcpu-alloc: 0 Built 1 zonelists in Zone order, mobility grouping off. Total pages: 2032 Kernel command line: bootargs="debug console=ttyAL0,115200" PID hash table entries: 32 (order: -5, 128 bytes) Dentry cache hash table entries: 1024 (order: 0, 4096 bytes) Inode-cache hash table entries: 1024 (order: 0, 4096 bytes) Memory available: 4696k/3377k RAM (1043k kernel code, 2333k data) NR_IRQS:32 Calibrating delay loop... why?:cry: 

If I comment out the calibrate_delay() in the main.c of kernel, I still stuck on the# Switching to clocksource timer#,see the result: 

... PID hash table entries: 32 (order: -5, 128 bytes) Dentry cache hash table entries: 1024 (order: 0, 4096 bytes) Inode-cache hash table entries: 1024 (order: 0, 4096 bytes) Memory available: 4696k/3377k RAM (1043k kernel code, 2333k data) NR_IRQS:32 pid_max: default: 4096 minimum: 301 Mount-cache hash table entries: 512 bio: create slab <bio-0> at 0 Switching to clocksource timer  

regards
Altera_Forum
Honored Contributor I
78 Views

 

--- Quote Start ---  

Memory available: 4696k/3377k RAM (1043k kernel code, 2333k data) 

--- Quote End ---  

 

Still doesn't look good to me - available should be less than total.
Altera_Forum
Honored Contributor I
78 Views

Thanks for your recommend, but I think it's may not a problem, see here: 

http://www.alterawiki.com/wiki/uclinuxdist 

... 

Memory available: 30136k/2333k RAM, 0k/0k ROM (1552k kernel code, 781k data) Mount-cache hash table entries: 512 

... 

regards
Altera_Forum
Honored Contributor I
78 Views

Has there been any resolution on this issue? I'm having the same problem on startup, but only when I boot from the EPCS memory -- from JTAG everything works smoothly. 

 

On the BlackFin mailing list, there seems to be a clue: 

<uclinux.org/pub/uClinux/archive/7256.html

 

Note that in my current design, if the TIMER_1MS_IRQ is 0 (that is, the IRQ used for the system timer throughout the uCLinux timex.h support), my system doesn't get past printing out "Ok, booting the kernel" 

 

However, if the IRQ is greater then 0, then the system boots until it gets to "Calibrating delay loop..." then hangs. 

 

Any thoughts would be appreciated.
Altera_Forum
Honored Contributor I
78 Views

So having chased this problem down a little further, apparently the system timer never fires its interrupt. It is initialized, and ioremapped to the correct address span, but a printk statement in the timer interrupt itself is never printed. 

 

Note that this only happens when I boot from EPCS flash. When I run from the JTAG everything works well. This is really curious...
Altera_Forum
Honored Contributor I
78 Views

Hello, 

This is problem is solved, because I have a small sdram(8 M),and I download it with file system, it's quite big for the small sdram, so I tried to just run the fake kernel, then I can see the kernel complain that can not mount a valid root file system, I'm sure it's because the lack of sdram, so I upgrade my board's sdram to 16M(I just can replace to this size), then it works well! 

see the result: 

Linux version 3.1.0-rc9-01179-ge9ea972 (liunx@gentoo) (gcc version 4.1.2)# 211 Sun Nov 13 06:55:01 CST 2011 bootconsole enabled early_console initialized at 0xe0800000 On node 0 totalpages: 4096 free_area_init_node: node 0, pgdat d033b2bc, node_mem_map d0350980 DMA zone: 32 pages used for memmap DMA zone: 0 pages reserved DMA zone: 4064 pages, LIFO batch:0 pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 pcpu-alloc: 0 Built 1 zonelists in Zone order, mobility grouping off. Total pages: 4064 Kernel command line: root=/dev/mtdblock0 rw rootfstype=jffs2 PID hash table entries: 64 (order: -4, 256 bytes) Dentry cache hash table entries: 2048 (order: 1, 8192 bytes) Inode-cache hash table entries: 1024 (order: 0, 4096 bytes) Memory available: 12812k/3385k RAM (1254k kernel code, 2130k data) NR_IRQS:32 Calibrating delay loop... 24.32 BogoMIPS (lpj=121600) pid_max: default: 4096 minimum: 301 Mount-cache hash table entries: 512 bio: create slab <bio-0> at 0 Switching to clocksource timer JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc. msgmni has been set to 25 io scheduler noop registered io scheduler deadline registered io scheduler cfq registered (default) ttyJ0 at MMIO 0x800000 (irq = 2) is a Altera JTAG UART console enabled, bootconsole disabled console enabled, bootconsole disabled 0.flash: Found 1 x16 devices at 0x0 in 8-bit bank. Manufacturer ID 0x000089 Chip ID 0x000017 Intel/Sharp Extended Query Table at 0x0031 Intel/Sharp Extended Query Table at 0x0031 Using buffer write method cfi_cmdset_0001: Erase suspend on write enabled Mem: 8272K used, 6388K free, 0K shrd, 0K buff, 5168K cached CPU: 0.0% usr 1.7% sys 0.0% nic 98.2% idle 0.0% io 0.0% irq 0.0% sirq Load average: 0.15 0.09 0.04 1/16 38 PID PPID USER STAT VSZ %MEM CPU %CPU COMMAND 38 33 root R 1980 13.4 0 1.5 top 33 1 root S 1980 13.4 0 0.0 -/bin/sh 1 0 root S 1884 12.7 0 0.0 /init 6 2 root SW 0 0.0 0 0.0 2 0 root SW 0 0.0 0 0.0 13 2 root SW 0 0.0 0 0.0 14 2 root SW 0 0.0 0 0.0 3 2 root SW 0 0.0 0 0.0 4 2 root SW 0 0.0 0 0.0 5 2 root SW 0 0.0 0 0.0 7 2 root SW< 0 0.0 0 0.0 8 2 root SW 0 0.0 0 0.0 9 2 root SW 0 0.0 0 0.0 10 2 root SW< 0 0.0 0 0.0 11 2 root SW 0 0.0 0 0.0 12 2 root SWN 0 0.0 0 0.0 root:/> regards:D
Altera_Forum
Honored Contributor I
78 Views

Thanks for the response!  

 

That's an interesting solution, and from what I've read (on blogs, etc) this type of problem seems to have non-intuitive answers. 

 

That being said, I have 64MB of memory. :) So it appears we have two different problems. 

 

Using the processor control registers, I was able to turn off interrupts and verify that the system timer was sending an interrupt to the processor at the correct time. As soon as I enable interrupts again, however, the interrupt thread (level sensitive) immediately jumps off to parts unknown. :evil:
Altera_Forum
Honored Contributor I
78 Views

Found the issue (obvious in hindsight): 

 

The exception vector hardcoded in the NIOS core was pointing to the EPCS Flash memory, because I was thinking that for each exception, I wanted to restart the processor. However, since interrupts are handled as exceptions through the internal interrupt controller, I was jumping to an address in the EPCS and hanging. 

 

Once I changed the exception vector to be the 0x20 offset into my main instruction memory, my problem went away, since the correct ISR was being called.
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