non-blocking AvMM reads

[Altera_Forum]

Hi, 

 I have observed that when user application tries to read from a non-existing address the uC hangs, but when doing the same with memory viewer in debug mode, it doesn't. I would assume the debugger is using a different instruction (with some sort of timeout) for read accesses. Is it possible to use the same in user application?  Thanks!

[Altera_Forum]

The JTAG debugger uses the same instructions as 'normal' code. 

IIRC the avalon cycle usually completes and returns ~0. I think there is a menu somewhere to enable a interrupt on an Avalon cycle with an illegal address (but it might be on the 'hidden' options menu). I've seen problems where such accesses from PCIe 'trash' the PCIe link - but only on one of the many BARs out system has.

[Altera_Forum]

Thanks dsl, I'm one step closer :-)  

but that option is "so well hidden", I couldn't find anything yet... any idea what keyword I should be looking for?

[Altera_Forum]

Indeed, you probably have to ask your FAE how to access the nios 'hidden config menu'. 

It contains some useful stuff - some of which probably generates broken cpus. We found out about it because I needed to disable dynamic branch prediction.