I'm trying to assign some sane addresses to memory and I/O blocks.
Whenever I put 'tightly coupled' code or data at a lower address than the general code/data master I get a warning about non-optimal logic.
This happens when there are only 2 slaves (one on each master) and the addresses could be split using a single address bit.
The design has several tightly coupled code and data blocks (2 Nios cpu), some IO accessible through the data master, and a 16MB SDRAM for buffers.
There is no data cache, the instruction master (+cache) is only present in case we want to use the JTAG debugger.
Ideally I'd like to setup something like:
0-64k: tightly coupled code.
64-128k: tightly coupled data.
128k-256k: I/O
16M-32M: SDRAM.
So that the layout is resonably independant of the size of the SDRAM.
%gp would be set to the 128k boundary, so that much of the data and I/O can be accessed with %gp relative instructions.
But the SOPC builder complains unless I put the SDRAM at address 0.
