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Altera_Forum
Honored Contributor I
1,154 Views

offset binary to signed converter for ADC

Hello 

I’m neebie in VHDL. I’m trying to build a simple radio receiver: CAN , mult, filter, I Q demod in Cyclone III , with quartus . I ‘m sorry for this question here, be I don’t found solution, after many searches. I’d like to convert the input data from CAN (offset binary) to signed value. Very common issue...At the end I’d like to do the conversion from signed to offset inary .  

Thus I try next code ( only on 3 bits for investigation purpose). Compilation ok, building component ok , starting simulation Ok ; but result Is the same as input…I ‘ don’t understand. Many thanks for your help. 

 

 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

USE ieee.std_logic_arith.all; 

ENTITY convsign IS 

PORT (op1 : IN UNSIGNED(2 DOWNTO 0); 

resu : OUT SIGNED(2 DOWNTO 0)); 

END convsign; 

ARCHITECTURE cpcvsign OF convsign IS 

BEGIN 

resu <= CONV_SIGNED(op1, 3); 

END cpcvsign;
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5 Replies
Altera_Forum
Honored Contributor I
78 Views

A good suggestion would be to study VHDL. There are lots of textbooks out there. One example is the book "the desingner's guide to vhdl (http://www.amazon.com/designers-guide-vhdl-systems-silicon/dp/1558602704)" from Peter Ashenden.

Altera_Forum
Honored Contributor I
78 Views

To convert offset binary to signed, just invert sign bit, nothing else

Altera_Forum
Honored Contributor I
78 Views

Invert the sign bit is the solution i use with logical gates, before my investigation on CONV_SIGNED fnction. 

I stop trying to understand convert function. I keep the basic solution in vhdl : 

 

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; 

use IEEE.STD_LOGIC_ARITH.ALL; 

use IEEE.STD_LOGIC_UNSIGNED.ALL;  

 

ENTITY INVBITBUS IS 

PORT( 

a_bus : IN bit_vector(2 downto 0); 

s_bus : OUT bit_vector(2 downto 0)); 

SIGNAL a, b ,c : BIT; 

END INVBITBUS ; 

ARCHITECTURE dataflow OF INVBITBUS IS 

BEGIN 

 

a <= a_bus(2); 

b <= a_bus(1); 

c <= a_bus(0); 

 

s_bus (2) <= NOT (a); 

s_bus (1) <= b; 

s_bus (0) <= c; 

 

END dataflow ;
Altera_Forum
Honored Contributor I
78 Views

As most problems, it can be solved in one line. VHDL-wise, the conversion can be most easily done as a XOR operation with an inversion mask.  

 

data2 <= data1 XOR x"800"; -- for 12 Bit data
Altera_Forum
Honored Contributor I
78 Views

hello 

as most problem , there many solutions..here is mine , simplier for 14 bits than the previous i have done....interresting for partial bus allocation. 

 

ENTITY INVBITBUS14 IS 

PORT( 

a_bus : IN bit_vector(13 downto 0); 

s_bus : OUT bit_vector(13 downto 0)); 

SIGNAL a13 : BIT; 

END INVBITBUS14 ; 

 

ARCHITECTURE dataflow OF INVBITBUS14 IS 

BEGIN 

 

a13 <= a_bus(13);  

s_bus (13) <= NOT (a13); -- inversion du bit 

s_bus(12 DOWNTO 0) <= a_bus(12 DOWNTO 0); 

 

END dataflow ; 

 

Many thanks for your help!!!!!!!!