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optimize ADC Code

Altera_Forum
Honored Contributor II
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Hi, I´m new in FPGA programming. 

I must read the ADC from the De0-Nano Board.I helped me with the Demo Code from the ADC-Demo at the CD. 

 

#define START_FLAG 0x8000 //1000 0000 0000 0000# define DONE_FLAG 0x8000 //1000 0000 0000 0000 alt_u16 ADC_Read(alt_u8 NextChannel){ //Wiedergabewert 16bit ( Übergabewert 8bit) int bDone = FALSE; alt_u16 Data16, DigitalValue = 0; // 16bit Data16 const int nMaxWait = 10; //Konstante nMaxWait = 1000 int nWaitCnt = 0; // start Data16 = NextChannel; //Data16 = Übrgabewert (zu lesneder Kanal) IOWR(READ_ADC_BASE, 0, Data16); //schreibe zu lesender Kanal Data16 |= START_FLAG; // Data 16 -> Startflag IOWR(READ_ADC_BASE, 0, Data16); // Übertragung starten // wait done while(!bDone && nWaitCnt++ <= nMaxWait){ //Schleife hört auf wenn bDone = true oder nWaitCnt >=nMaxWait Data16 = IORD(READ_ADC_BASE,0); //Data16 = Wert des Kanals bDone = (Data16 & DONE_FLAG)?TRUE:FALSE; //Vergleich Kanal mit Done_Flag } if (bDone) // Wenn Data16 = DONE_FLAG -> Data16 Null schreiben DigitalValue = Data16 & 0xFFF; // 12 bits // stop IOWR(READ_ADC_BASE, 0, 0); //Kanal löschen return DigitalValue; //DigitalValue zurückgebenSorry but the commends are in German but that´s doesn´t matter I think. 

Could this Code be run faster or can i optimize it?  

 

In the Main Program I only run a loop which channel i want to read. 

 

thx everybody for help Stefan
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