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Altera_Forum
Honored Contributor I
1,170 Views

principle of acquisition f=10MHz signal with nios software

Hi,  

i'm working on nios and i would like to acquire a signal that f=10MHz. 

I've a clock turning on 100MHz. 

I've tried many ways such as getting signal from main function. But the frequency that main function is called is not more than 300kHz. 

The other way was using an interruption with timer. But i can't understand the principle of timer, because it just interrupts main function while the counter reaches 0. So main function will not detect it because of it's frequency which is slower than timer's. 

 

int main(){ IOWR_ALTERA_AVALON_TIMER_PERIODL(TIMER_0_BASE, 0xa); --100MHz/10MHz=10=0xa IOWR_ALTERA_AVALON_TIMER_PERIODH(TIMER_0_BASE, 0); //set RUN, set CONTuous, set ITO IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMER_0_BASE, 7); //register the interrupt (and turn it on) alt_irq_register(TIMER_0_IRQ, (volatile int*)&flag, timer_isr); while(){ } } static int timer_isr(volatile int* context, alt_u32 id){ --i've changed static void to static int to be able to write outport IOWR_ALTERA_AVALON_TIMER_STATUS(TIMER_0_BASE, 0); //reset TO flag *context = *context + 1 ; IOWR_ALTERA_AVALON_PIO_DATA(PIO_OUT_BASE, context); }  

 

So i need your help and ideas. Thanks
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7 Replies
Altera_Forum
Honored Contributor I
21 Views

When u say acquire a signal: are u talking about make a/d conversions and stores in ram? Or simply measure its frequency?

Altera_Forum
Honored Contributor I
21 Views

There is LPM_SHIFTREG megafunction. You could make from your fast 10 MHz input signal an internal wider and slower one. Let's say 32 times wider and then main function with 300 kHz perhaps could do the job.

Altera_Forum
Honored Contributor I
21 Views

 

--- Quote Start ---  

When u say acquire a signal: are u talking about make a/d conversions and stores in ram? Or simply measure its frequency? 

--- Quote End ---  

 

 

Thanks for your reply. 

 

The received data (10MHZ) must be stored to sdram. It's a 8 bit dac. I read about dma to store directly to the ram without passing through the nios processor. But i couldn' t found any example to apply it.
Altera_Forum
Honored Contributor I
21 Views

 

--- Quote Start ---  

There is LPM_SHIFTREG megafunction. You could make from your fast 10 MHz input signal an internal wider and slower one. Let's say 32 times wider and then main function with 300 kHz perhaps could do the job. 

--- Quote End ---  

 

 

Thanks. My signal has 8 bits so it's datarate is 8*10MHz=80MHz and i have no so many input pins to parallelize them all.
Altera_Forum
Honored Contributor I
21 Views

I take a look at your C code and I understand what u're trying to do. Read a byte on each interrupt, but the overhead slow down the performance. A hardware solution is the right way. I don't know how to use DMA component of Nios, too. 

 

If you have SRAM in your system ( not SDRAM, SRAM ), you can implement a simple state machine that when it is triggered acquires de sample, store them in RAM and when finishes make it know to the nios processor. The nios can interface with the SRAM ( to read the samples ) with IO ports. This is not an elegant solution but it should work. You can make it with a SDRAM, too, but it is harder. 

 

How many byte are you storing in SDRAM?
Altera_Forum
Honored Contributor I
21 Views

 

--- Quote Start ---  

I take a look at your C code and I understand what u're trying to do. Read a byte on each interrupt, but the overhead slow down the performance. A hardware solution is the right way. I don't know how to use DMA component of Nios, too. 

 

If you have SRAM in your system ( not SDRAM, SRAM ), you can implement a simple state machine that when it is triggered acquires de sample, store them in RAM and when finishes make it know to the nios processor. The nios can interface with the SRAM ( to read the samples ) with IO ports. This is not an elegant solution but it should work. You can make it with a SDRAM, too, but it is harder. 

 

How many byte are you storing in SDRAM? 

--- Quote End ---  

 

 

I've already tried your version that works well with sram without niosii. But my principle purpose is to get 2 port access to sdram via nios using c language. I've no any sdram controller core so i decided to pass by nios.  

There is a thing that i can't understand: how the nios makes vga core to work? because the min frequency that must be created is 25MHz? so it can generate high frequency and apply it to nios system output. But it's not explained in any altera document. Am I right?
Altera_Forum
Honored Contributor I
21 Views

I don't know how to use nios vga controller. But I read in a book how to make it. Resolution 640 x 480 8 bit color depth. It uses a 512K SRAM ( as frame buffer ) because timing scheme it's easier than SDRAM. 

 

The fpga has a 50 MHz clock, so a pixel tick slow down to 25 MHz. Also, this pixel tick switch the address of the memory between the cpu and the vga controller. So, it's like a dual port access. But multiplexed in time. A state machine place the read and write signal of the cpu in the proper clock cycles.