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Altera_Forum
Honored Contributor I
2,111 Views

problem- TSEMAC SW reset bit never cleared!

hi, 

im using cyclone 3 and a phy of marvell in order to implement Ethernet.  

(nios2, tse from sopc). when the software starts, i get this message: 

TSEMAC SW reset bit never cleared! 

i try to ping and it doesnt work, i get no response and the server dosent react. 

i used the software example(simple soket sever) and i did a very simler design to the example. 

i would appreciate any help  

thanks 

sharen
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16 Replies
Altera_Forum
Honored Contributor I
75 Views

Could you check all the clocks that are going to the TSE, including the ones for the interface with the PHY? One of them could be missing, and that would cause that kind of error message.

Altera_Forum
Honored Contributor I
75 Views

hi, 

all the clocks are connected exactly like the evaluation board, and they seem to be ok.  

the only diffrence is that im using a 25MHz clk (for 100M) and not 125M like the example.  

Sharen
Altera_Forum
Honored Contributor I
75 Views

hi, i solve that problem, it was a clk issue. now everything seems to be ok, i dont get a respons for ping, but with a sniffer (wireshark), i can see a replay from altera, with the expected mac adress, with protocol -ip, and in the info is written "Bogus IP length (2, less the header length 24)". 

i would appreciate any help or idea. 

thanks 

Sharen
Altera_Forum
Honored Contributor I
75 Views

Do you see the arp reply from the Nios first? Could you dump the packet contents here?

Altera_Forum
Honored Contributor I
75 Views

hi,  

the altra replays but not an arp but ip. 

what i get is the following: 

ping try: 

3F 76 00 07 ED FF 00 07 ED FF CD 15 08 00 06 04  

00 02 00 07 ED FF CD 15 0A 00 CD 15 0A 00 60 7B 

3F 76 0A 00 00 01 0A 00 00 01 17 03 80 10 00 00  

00 00 00 00 00 00 00 00 00 00 00 00  

Thanks  

Sharen
Altera_Forum
Honored Contributor I
75 Views

The IP header is wrong... could you do a signaltap capture on the TSE's Avalon Stream interfaces, and compare the data with what you capture on Wireshark?

Altera_Forum
Honored Contributor I
75 Views

i did debug in software and i saw the data that should be sent - it was a good message, but when i see it in the sniffer there is a shift of 4 bytes and some repetition in the middle of the message (of 4 bytes).. could something be wrong with the tx_dma?  

Thanks  

Sharen
Altera_Forum
Honored Contributor I
75 Views

hi, 

i tried to capture the data in signaltap but i cant see anything in the tx port (txd or tx_en with trigger), but i can still see some kind of a replay in Wireshark, Thats very stange, do you have any idea why or how can i make it work? 

(the mac is working in 100M means tx/rx 25M and im sampling with 100M) 

by the way if i give trigger to rx i can see the data that is recived by the mac. 

any help would be great! i have no idea! 

Thanks 

Sharen
Altera_Forum
Honored Contributor I
75 Views

I don't know why you don't see anything on the tx side... you should! Are you sure you are using a valid clock, and are triggering on the right condition? 

The problem could come from the DMA. You should try and monitor the Avalon Stream interfaces (between the DMAs and the TSE) to see if there is any problem there. 

How big are the TSE's tx and rx fifos?
Altera_Forum
Honored Contributor I
75 Views

in the FIFO options: 

Memory block -AUTO 

width - 32 bit 

Depth (for both rx and tx) 2048*32 

is that ok? 

the DMA should be connected to a descriptor memory and to another memory, what sould be the size of that memory(the the evaluation board of cyclone 3 they use DDR) ? 

Thanks 

Sharen
Altera_Forum
Honored Contributor I
75 Views

The size of the memory shouldn't matter, and the fifo is more than big enough. 

You really need to capture the Avalon Stream signals and compare them with what the software is trying to send to see what's going on.
Altera_Forum
Honored Contributor I
75 Views

i cant see the Avalon Stream signals also, it seems like they dont change i have no idea why. 

i use external memory SSRAM, does it matter? 

can i change the external memory to an on chip memory?  

Thanks  

Sharen
Altera_Forum
Honored Contributor I
75 Views

The memory type shouldn't matter. 

Are you sure you are looking at the transmit Avalon stream? Try to trigger on the 'valid' signal
Altera_Forum
Honored Contributor I
75 Views

hi, 

finally i could see the signal! and it is exactly what i see with the sniffer. 

so where could the problem be?? 

i saw in the exaple of altera that they work with DDR that uses rising and falling of the clk, and the sram doesnt.. is that a problem?  

( now the nios and sram are working in 50M and the tse mac, dma in 25M) 

Thanks 

Sharen
Altera_Forum
Honored Contributor I
75 Views

Could you do a copy/paste of what should be sent (what you see from the software) and what you see on the Avalon stream? (including the valid/ready/startofpacket/endofpacket signals) 

It could be a DMA or cache problem.
Altera_Forum
Honored Contributor I
75 Views

 

--- Quote Start ---  

hi, i solve that problem, it was a clk issue. now everything seems to be ok, i dont get a respons for ping, but with a sniffer (wireshark), i can see a replay from altera, with the expected mac adress, with protocol -ip, and in the info is written "Bogus IP length (2, less the header length 24)". 

i would appreciate any help or idea. 

thanks 

Sharen 

--- Quote End ---  

 

 

Could you send how you solve problem with clock?
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