problem with custom istruction: clk_en never changes

[Altera_Forum]

hello 

 i'm trying to do a multicycle custom instruction in oder to pilot a led.  my problem is the fact that the clk_en never takes the value '1', it always remains to '0' (seen from signaltab) and i don' know why. that is the code that i'm using : l     port  (  clk : in std_logic;  reset: in std_logic;  clk_en: in std_logic;  dataa : in std_logic_vector (31 downto 0);  datab : in std_logic_vector (31 downto 0);  result: out std_logic_vector (31 downto 0);  coe_conduitOn_export: out std_logic  ); end entity; architecture rtl of turnOn is -- RTL au lieu de led  signal result_i: std_logic_vector (31 downto 0);  signal zero :std_logic_vector(31 downto 0);  begin  process(clk)  begin  if(reset = '1') then  result <= (others=>'0');  coe_conduitOn_export<='0';  else  if(clk_en='1') then  if (rising_edge(clk))then  coe_conduitOn_export<= dataa(0);--dataa(0);  result <= dataa or datab;  end if;  else  result <= (others=>'0');  coe_conduitOn_export<='0';  end if;  end if;  end process;  please help me.

[Altera_Forum]

We can not tell you why the clk_en is stucking with 0 

Because that is an input. so, where it comes from? Do you know that?

[Altera_Forum]

Probably worth double-checking that you have added the custom instruction to the cpu, and that the code you have is actually trying to execute the instruction. 

I've only used combinatorial custom instructions. A simple one of those might be a good 'first test' since there is less to go wrong.  FWIW I've not actually verified that 'readra' and 'readrb' have any effect (ie whether setting them zero disables the pipeline stall against the source registers). writerc will have an effect (enables the register file update). The custom instruction itself can use any of the instruction fields and the values of the two source registers for any purpose, I've used the 'B' field as extra opcode bits.

[Altera_Forum]

akira, 

normaly once the macro of the custom instruction is used in the nios software, the clk_en would be engaged, i'm wrong?

[Altera_Forum]

There is an option/window somewhere on qsys that will display a gate level schematic of the fpga image. Although the cpu itself appears as a single 'blob', the mux around custom instructions and the way custom instructions are built is visible. This might be illuminating.

[Altera_Forum]

--- Quote Start ---  There is an option/window somewhere on qsys that will display a gate level schematic of the fpga image. Although the cpu itself appears as a single 'blob', the mux around custom instructions and the way custom instructions are built is visible. This might be illuminating.  --- Quote End ---    i don't see this option on qsys...i have built my system on SOPC builder...

[Altera_Forum]

basically, you can follow the signals in your QuartusII software. 

open tree in your ProjectNavvigator, and find your IP's source in your tree. ( it is in SOPCbuilders core)  as you can use signaltap, you can follow signals until it is connected secured IP core.

[Altera_Forum]

--- Quote Start ---  basically, you can follow the signals in your QuartusII software. open tree in your ProjectNavvigator, and find your IP's source in your tree. ( it is in SOPCbuilders core)  as you can use signaltap, you can follow signals until it is connected secured IP core.  --- Quote End ---    i have already done it but i see no changes on the signal clk_en