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Altera_Forum
Honored Contributor I
1,901 Views

provided SPL prevents Linux from booting

Hello all, 

 

I'm attempting to do some work at the SPL/U-Boot level, and am finding that when replacing the SPL preloader, it boots U-Boot OK, but when U-Boot passes control to zImage, it hangs. 

 

My environment is: 

DE1-SoC, rev F 

"Linux console" micro-SD card image from Terasic site 

Nothing loaded to the FPGA. 

Without any changes to that, everything boots fine, all the way to a Linux login prompt. 

I'll call that SPL, spl1

 

Since I need to develop around SPL, I tried replacing the SPL on the SD card with another I could rebuild from Terasic. 

That code is from their "DE1-SoC CD-ROM (rev.F Board)", 

in .../Demonstrations/SOC_FPGA/de1_soc_GHRD/software/spl_bsp/  

 

There is a prebuilt image there, preloader-mkpimage.bin (I'll call spl2). 

That boots through to the original U-Boot, but when trying to get to Linux, it hangs with:U-Boot SPL 2013.01.01 (Dec 20 2017 - 19:24:06) 

BOARD : Altera SOCFPGA Cyclone V Board 

CLOCK: EOSC1 clock 25000 KHz 

CLOCK: EOSC2 clock 25000 KHz 

CLOCK: F2S_SDR_REF clock 0 KHz 

CLOCK: F2S_PER_REF clock 0 KHz 

CLOCK: MPU clock 800 MHz 

CLOCK: DDR clock 400 MHz 

CLOCK: UART clock 100000 KHz 

CLOCK: MMC clock 50000 KHz 

CLOCK: QSPI clock 400000 KHz 

RESET: COLD 

INFO : Watchdog enabled 

SDRAM: Initializing MMR registers 

SDRAM: Calibrating PHY 

SEQ.C: Preparing to start memory calibration 

SEQ.C: CALIBRATION PASSED 

SDRAM: 1024 MiB 

ALTERA DWMMC: 0 

 

 

U-Boot 2013.01.01 (Oct 24 2013 - 17:40:22) 

 

CPU : Altera SOCFPGA Platform 

BOARD : Altera SOCFPGA Cyclone V Board 

DRAM: 1 GiB 

MMC: ALTERA DWMMC: 0 

In: serial 

Out: serial 

Err: serial 

Net: mii0 

Warning: failed to set MAC address 

 

Hit any key to stop autoboot: 0  

reading u-boot.scr 

** Unable to read file u-boot.scr ** 

Optional boot script not found. Continuing to boot normally 

reading zImage 

3809104 bytes read in 338 ms (10.7 MiB/s) 

reading socfpga.dtb 

18033 bytes read in 7 ms (2.5 MiB/s) 

fpgaintf 

ffd08028: 00000000 .... 

fpga2sdram 

ffc25080: 00000000 .... 

axibridge 

ffd0501c: 00000000 ....# # Flattened Device Tree blob at 00000100 

Booting using the fdt blob at 0x00000100 

Loading Device Tree to 03ff8000, end 03fff670 ... OK 

 

Starting kernel ... 

 

(and that's where it hangs) 

 

I also tried rebuilding the SPL from that directory. That spl3 had the same result. 

 

I tried using the DS-5/Eclipse debugger to see what was going on. I don't have symbols for that kernel AFAIK. When stopping execution, I could see some activity. However, if I let it run for another second, then I can no longer stop it. I get the error:ERROR(TAD9-NAL30):  

! Unable to stop device Cortex-A9_0 

! Cannot stop target. 

 

 

SPL3 is the point where I really need to be, so I can make source changes there. 

Any advice on clearing this up would be a huge help. 

Thanks, -- Tom
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7 Replies
Altera_Forum
Honored Contributor I
90 Views

Can you show the console output from the original (good) boot up to the point where it says "Starting kernel". I'm wondering if there is a difference in your clock settings, or in your device tree blob. Can you double check to make sure you are using the same DTB file in both cases?

Altera_Forum
Honored Contributor I
90 Views

Thanks for the reply. The output of the original SPL1 is less helpful I think - less detail. 

 

I tried booting SPL2 and 3 with both the original dtb, and a new dtb provided by Terasic on their SystemCD, from 

.../SystemCD/Demonstrations/SOC_FPGA/de1_soc_GHRD/soc_system.dtb 

The output is the same in both, except for the length of the dtb loaded, as quoted in my previous post. 

 

Do you happen to have a U-Boot or GDB debug script to display the clock settings? I could include that output too. 

 

Here is the boot output using the original SPL1 and the original DTB 

 

U-Boot SPL 2013.01.01 (Nov 04 2013 - 19:51:38)  

BOARD : Altera SOCFPGA Cyclone V Board  

SDRAM: Initializing MMR registers  

SDRAM: Calibrating PHY  

SEQ.C: Preparing to start memory calibration  

SEQ.C: CALIBRATION PASSED  

ALTERA DWMMC: 0  

 

 

U-Boot 2013.01.01 (Oct 24 2013 - 17:40:22)  

 

CPU : Altera SOCFPGA Platform  

BOARD : Altera SOCFPGA Cyclone V Board  

DRAM: 1 GiB  

MMC: ALTERA DWMMC: 0  

In: serial  

Out: serial  

Err: serial  

Net: mii0  

Warning: failed to set MAC address  

 

Hit any key to stop autoboot: 0  

reading u-boot.scr  

** Unable to read file u-boot.scr **  

Optional boot script not found. Continuing to boot normally  

reading zImage  

3809104 bytes read in 1283 ms (2.8 MiB/s)  

reading socfpga.dtb  

17119 bytes read in 13 ms (1.3 MiB/s)  

fpgaintf  

ffd08028: 00000000 ....  

fpga2sdram  

ffc25080: 00000000 ....  

axibridge  

ffd0501c: 00000000 ....  

# # Flattened Device Tree blob at 00000100  

Booting using the fdt blob at 0x00000100  

Loading Device Tree to 03ff8000, end 03fff2de ... OK  

 

Starting kernel ...  

 

Booting Linux on physical CPU 0x0  

(clean boot)
Altera_Forum
Honored Contributor I
90 Views

Sorry I don't have a debugger script for you. However, if you have the SoC-EDS Arm DS-5 license, you should be able to debug this problem using the HPS JTAG port.  

 

It looks like the SPL source code base is the exact same version (2013.01.01) but I suppose when you rebuilt it, the environment was a bit different (no CLOCK setting printed out). Maybe you can turn on debug prints for another SPL build? I tried it once and the image turned out to be too big so it failed. Maybe it will work for you? You can also add in your own printf statements.  

 

So, at the point where Uboot says "Starting kernel", there's no indication that the zImage file was located (or not). Can you verify it's in the right place based on your BSP editor settings? I'm wondering what Uboot says when it can't find the zImage. Maybe try deleting the image on purpose to see what happens?
Altera_Forum
Honored Contributor I
90 Views

Here are the clock manager registers from runs of both SPL1 and SPL2. 

Maybe there is a script to display them (much) better, but for now it's easy to see that there are a few differences. 

Am not sure which might be relevant.... 

 

I will also note that U-Boot's mtest does not work in either SPL when testing SDRAM addresses, 

though it does when testing OCRAM. 

 

 

Via SPL1: 

 

# Clock Manager 

SOCFPGA_CYCLONE5# md ffd04000 6  

ffd04000: 00000004 00000000 000001ff 00000000 ................  

ffd04010: 00000003 00000000 ........  

 

# Main PLL Group 

SOCFPGA_CYCLONE5# md ffd04040 e  

ffd04040: 000001fa 00004002 00000000 00000000 .....@..........  

ffd04050: 00000000 00000003 00000003 0000000f ................  

ffd04060: 000003ff 00000095 00000004 00000000 ................  

ffd04070: 00000003 00000000 ........  

 

# Peripheral PLL Group 

SOCFPGA_CYCLONE5# md ffd04080 d  

ffd04080: 0001027a 00004002 00000003 00000003 z....@..........  

ffd04090: 00000001 00000013 00000004 00000009 ................  

ffd040a0: 00000fff 00000240 00001869 0000001a ....@...i.......  

ffd040b0: 00000000 ....  

 

# SDRAM PLL Group 

SOCFPGA_CYCLONE5# md ffd040c0 8  

ffd040c0: 000000fa 00004002 00000001 00000000 .....@..........  

ffd040d0: 00000001 00000005 0000000f 00000000 ................  

 

Via SPL2: 

 

# Clock Manager 

SOCFPGA_CYCLONE5# md ffd04000 6  

ffd04000: 00000004 00000000 000001c7 00000000 ................  

ffd04010: 00000003 00000000 ........  

 

# Main PLL Group 

SOCFPGA_CYCLONE5# md ffd04040 e  

ffd04040: 000001fa 00004002 00000000 00000000 .....@..........  

ffd04050: 00000000 00000003 000001ff 0000000f ................  

ffd04060: 000003ff 00000095 00000004 00000000 ................  

ffd04070: 00000003 00000000 ........  

 

 

# Peripheral PLL Group 

SOCFPGA_CYCLONE5# md ffd04080 d  

ffd04080: 0000013a 00004002 000001ff 00000003 :....@..........  

ffd04090: 000001ff 00000004 00000004 000001ff ................  

ffd040a0: 00000fff 00000900 00001869 0000001a ........i.......  

ffd040b0: 00000000 ....  

 

# SDRAM PLL Group 

SOCFPGA_CYCLONE5# md ffd040c0 8  

ffd040c0: 000000fa 00004002 00000001 00000000 .....@..........  

ffd040d0: 00000001 00000005 0000000f 00000000 ................
Altera_Forum
Honored Contributor I
90 Views

My goal is to build a working SPL. This version from the Terasic SystemCD is the only (partial) success I've had. So I can't build other versions, because there doesn't appear to be out-of-the-box support for de1-soc. The SystemCD builds SPL by grabbing U-boot from the embedded distro, and patching it. So, I can add print statements or whatever to SPL2, but I don't have much of a clue what to print. 

 

The U-boot script for loading and boot doesn't change at all in my testing. In the output I quoted, you can see: 

reading zImage 

3809104 bytes read in 1283 ms (2.8 MiB/s) 

reading socfpga.dtb 

17119 bytes read in 13 ms (1.3 MiB/s) 

 

It always gets loaded to the same place, 0x8000
Altera_Forum
Honored Contributor I
90 Views

I'm learning this stuff too so take this with a grain of salt... 

Since you are wanting to customize SPL, I think you will have no choice but to learn a bit of the U-boot code (how and what to modify). So, you should load all of the code in Eclipse (DS-5 version, or any other) as a project so that it can index the code for you. Then you get all of the usual IDE features. This should help: 

https://community.nxp.com/thread/222791 

 

I think you should really focus on why SPL1 and SPL2 register settings don't match (Clock Manager, Main PLL Group, Peripheral PLL Group). The output of the "md" commands is very helpful. You control all of the clock settings in the Qsys project so if you can find the project associated with SPL1, you should compare it to your custom SPL2 Qsys project.
Altera_Forum
Honored Contributor I
90 Views

Well, I'm not a Qsys user, so I wouldn't know where to start looking for an SPL Qsys project file. Regarding the clocks, I did use U-Boot, after SPL2, to change all of the clocks settings to what they would have been had SPL1 run. Same problem. 

 

I should be able to pick up the code that Terasic used to build SPL, and build it myself. Then I could introduce the changes I want. I'm assuming that the Terasic version of SPL is in: 

.../SystemCD/Demonstrations/SOC_FPGA/de1_soc_GHRD/software/spl_bsp/ 

 

Does anyone know if that's right? 

 

Terasic?