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purpuse of waitrequest

Altera_Forum
Honored Contributor II
859 Views

Hello 

 

I've designed a custom component which acts as an Avalon Slave. This component has a 32-bit result-register. If data are valid or not is indicated by Bit 31 (true (1) = data valid). Now I want to upgrade the component in such a way that read access to the result register clears the valid bit (write 0 to bit 31).  

How can i avoid a write acces at the same time to the valid bit? I mean, the avalon master and my IP-Core could try to write at the same time to the register. 

Can I use "waitrequest"? The IP-Core updates the register is in a specific state of the fsm. Can I set the waitrequest signal high in this state and everything would be fine? Or has waitrequest an other purpose? 

 

Thank you  

brunjak
0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
105 Views

 

--- Quote Start ---  

 

I've designed a custom component which acts as an Avalon Slave. This component has a 32-bit result-register. If data are valid or not is indicated by Bit 31 (true (1) = data valid). Now I want to upgrade the component in such a way that read access to the result register clears the valid bit (write 0 to bit 31).  

How can i avoid a write acces at the same time to the valid bit? I mean, the avalon master and my IP-Core could try to write at the same time to the register. 

Can I use "waitrequest"? The IP-Core updates the register is in a specific state of the fsm. Can I set the waitrequest signal high in this state and everything would be fine? Or has waitrequest an other purpose? 

 

--- Quote End ---  

The read or write command to the register is accepted by the component deasserting waitrequest. If you assert waitrequest when your other logic is modifying the register, then you will stall any concurrent access by an Avalon-MM master. 

 

So yes, you can use waitrequest to implement the functionality you want. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor II
105 Views

Thank you for your help.  

 

After studing the avalon specification again I have a few question more.  

1) Is it correct that a "normal" read or write-access needs two cycles? 

2) Can I simulate the read and write behaviour with ModelSim? Is there a master aviable? 

 

Thank you 

brunjak
Altera_Forum
Honored Contributor II
105 Views

 

--- Quote Start ---  

 

After studing the avalon specification again I have a few question more.  

1) Is it correct that a "normal" read or write-access needs two cycles? 

 

--- Quote End ---  

No. If a device has waitrequest low, then a write will be accepted in one cycle. The read command will also be accepted in one cycle. The Avalon specification indicates that a slave cannot deassert wait and assert readdatavalid in the same clock cycle, so the soonest a slave can return read data is one clock after the waitrequest is deasserted, i.e., two clock cycles for a single-read. However, a burst read can overlap the acceptance of the next read command while delivering the read data from a previously accepted command, if your read burst is long enough, then reads are essentially one clock too. 

 

 

--- Quote Start ---  

 

2) Can I simulate the read and write behaviour with ModelSim? Is there a master aviable? 

 

--- Quote End ---  

Yes, there is a SystemVerilog JTAG-to-Avalon-MM BFM. If you are using the Altera Starter Edition, then your testbench will also need to be in SystemVerilog (or Verilog). 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor II
105 Views

Thank you for your explanation. 

 

Ragards 

brunjak
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