Hi!
I have a question about using the DDR2 SDRAM in my DSP Development Kit, Cyclone III Edition. I've built a Nios II system in SOPC Builder and I've included the component DDR2 SDRAM High Performance Controller. In the Parameter Settings I've chosen the Memory Preset "Micron MT47H32M16CC-3 X4 + MT47H32M8BP-3 X1" because they are the chips of my board. In "PLL reference clock frequency" I've put 50MHz and in "Memory clock frequency" 150 MHz. The rest of the parameters I left the default. Is that correct? I have 4 warnings in SOPC Builder: - cpu_0: The address range of the slaves connected to the Nios II instruction master exceeds 28 bits. Attempts to call functions across 28-bit boundaries is not supported by GCC and will result in linker errors. - altmemddr_0.s1: Signal local_be[18] of type byteenable must have width [1, 2, 4, 8, 16, 32, 64, 128] - altmemddr_0.s1: readdata[144] width must be in {8, 16, 32, 64, 128, 256, 512, 1024} for dinamic addressing - altmemddr_0.s1: writedata[144] width must be in {8, 16, 32, 64, 128, 256, 512, 1024} for dinamic addressing Why do I get this warnings? When I generate the system I get the next error: "slave data width(144) for slave altmemddr_0/s1 unexpected" Moreover, in Quartus II I execute the tcl script altmemddr_0_phy_assignments.tcl. In the Pin Planner I get the pins of the SDRAM, but I don't know what location put in some of them because in my board there are two banks of memory (top and bottom), but the pins i get in the Pin planner do not refer to bottom or top. My version of Quartus II is 10.0sp1. Thanks to all.Link Copied
For more complete information about compiler optimizations, see our Optimization Notice.