"FIFO Interface" component support

[Altera_Forum]

Here's the place to talk about the FIFO interface component that I just posted. Fire away!

[Altera_Forum]

Hi Mike, 

 I haven't installed your IP yet, but after reading your post I had the silly question of how is your component better than just using a lpm_fifo?  I'm not saying it isn't, I'm just wanting to learn. I hooked up an lpm_fifo with IUL and IRQ on almost_full, and want to know what that approach lacks. It seemed to work pretty well.  I've had trouble achieving 100% on both Streaming DMA and driving a Master Port. Would your component be a good buffer for either of these to avoid that 1% loss?  Thanks, Ken

[Altera_Forum]

--- Quote Start ---  originally posted by kenland+aug 2 2004, 04:48 pm--><div class='quotetop'>quote (kenland @ aug 2 2004, 04:48 pm)</div>  --- quote start ---  i haven&#39;t installed your ip yet, but after reading your post i had the silly question of how is your component better than just using a lpm_fifo?  i&#39;m not saying it isn&#39;t, i&#39;m just wanting to learn.  i hooked up an lpm_fifo with iul and irq on almost_full, and want to know what that approach lacks. it seemed to work pretty well.[/b]  --- quote end ---   hahaha... now that you mention it, an iul instance would cover about half the cases that my fifo interface does; that&#39;s probably why nobody else did this yet. i didn&#39;t think of the flag-to-interrupt connection because my design doesn&#39;t use interrupts. you still have to instantiate an lpm_fifo or somesuch with mine; i take it i didn&#39;t make that clear enough in the docs?  as for what&#39;s different, here&#39;s what i could think of: [list][*]streaming mode should benefit if you&#39;re reading from a legacy-mode fifo, since iul doesn&#39;t do latency.   [*]used words/free words registers and thresholds.   [*]end-of-packet detection.   [*]can read and/or interrupt on more than one flag, and can change interrupt masks at runtime.   [*]one peripheral instead of two or three.   [*]can block master when writing to full fifo or reading empty fifo.   [*]at some point, i&#39;ll have a character driver for it, so it can work like a uart for interprocessor communication.   [*]on a dual-clock fifo, you don&#39;t have almost-full or almost-empty.   [*]it&#39;s all prefab; you don&#39;t have to recheck the timing every time. [/list]so basically, you could do almost everything that fifo interface does with an iul, a couple pios (one for flags and one for usedw[]), and a bunch of external logic. it would just be more work.  personally, i&#39;m not a big fan of iul; it took me quite a bit of searching to find the difference between avalon register slave and avalon memory slave; there&#39;s a cool interface for defining ports, but no way to define parameters passed to the top-level entity; and there&#39;s no way to define more than one port (e.g. one iul with both master and slave ports).  <!--quotebegin-kenland@Aug 2 2004, 04:48 PM i&#39;ve had trouble achieving 100% on both streaming dma and driving a master port.  would your component be a good buffer for either of these to avoid that 1% loss?  --- Quote End ---   I can&#39;t say without knowing what the 1% loss is from...

[Altera_Forum]

Hi Mike, 

 Your docs were fine and it was clear that I had to instantiate my own fifo.  Well I built a system with your FIFO. One request is that the port names be shortened, they caused my SOPC block to grow in width and break all of my connections. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif   I went over the next iteration of our prototype design this morning with the HW guy. He really wants to pursue a fifo based approach for streaming data into the Nios. When I get his new logic I&#39;ll wire it up to your fifo port and give it a whirl! I think your point about the dc fifo not having an AlmostFull flag will be important for our application.  Not sure when this will be, but I&#39;ll buzz in with my comments.  I&#39;d like to make a dummy data generator that you give it a data rate and it spits data into your fifo port at that rate. It would be great for testing and verification.  Ken

[Altera_Forum]

--- Quote Start ---  originally posted by kenland@Aug 3 2004, 12:35 PM well i built a system with your fifo.  one request is that the port names be shortened, they caused my sopc block to grow in width and break all of my connections.  --- Quote End ---   Man, the way they name ports (maybe I should post a patch to remove the word "the" everywhere?), I don&#39;t see how I&#39;d have any reasonable control over component width. So will omitting the "fifo_" prefix do it for you? Anyone else think it should stay?    --- Quote Start ---  originally posted by kenland@Aug 3 2004, 12:35 PM i&#39;d like to make a dummy data generator that you give it a data rate and it spits data into your fifo port at that rate.  it would be great for testing and verification.  --- Quote End ---   Sounds good. With or without an actual FIFO being involved? If a FIFO isn&#39;t involved, the timing might not be right. The real trick is going to be generating the dummy data.  Forgot to mention... one of the reasons I made this component is because I have a parallel ADC in my system. So I&#39;ll need the CPU to configure the ADC, then turn the ADC on and DMA its data through to the FIFO. Also, the CPU needs to write to the FIFO whether or not the ADC is streaming to it (I have flag bits in the data words which allow the streams to get mixed together). Imagine what I&#39;d have to write if I didn&#39;t have DMA or the switched fabric/multi-master bus...

[Altera_Forum]

Mike, 

 That&#39;s ok, I fixed the name length myself. (with right-click->rename in SOPC Builder http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/rolleyes.gif )  Yeah, my system has 6MSPS 10bit/sample ADC. I&#39;ll bet that&#39;s is very common to have a need to stream data into a Nios for processing. That&#39;s why I was so surprised Altera didn&#39;t have a better canned solution or at least an example.  I&#39;m the master of dummy loads. That&#39;s about all I&#39;ve learned to do. The real stuff I have to rely on you HW types.   But I think an example that would excercise your port would be a great addition to get people up and running quickly. Just because I&#39;ve wasted a few months attempting this doesn&#39;t mean others should have to. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif   Ken

[Altera_Forum]

--- Quote Start ---  originally posted by kenland@Aug 3 2004, 10:16 PM that&#39;s ok, i fixed the name length myself. (with right-click->rename in sopc builder  http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/rolleyes.gif )  --- Quote End ---   Oh, you meant the component name, not the port names. Gah, I need to find what PTF thing I left out. The SOPC tutorial pretty much tells everyone that they should rename the components after creating them. I&#39;m wondering why they don&#39;t just put you right into rename mode after you add a component...    --- Quote Start ---  originally posted by kenland+aug 3 2004, 10:16 pm--><div class='quotetop'>quote (kenland @ aug 3 2004, 10:16 pm)</div>  --- quote start ---  yeah, my system has 6msps 10bit/sample adc.  i&#39;ll bet that&#39;s is very common to have a need to stream data into a nios for processing.  that&#39;s why i was so surprised altera didn&#39;t have a better canned solution or at least an example.[/b]  --- quote end ---   seeing how a super-simple fifo interface like the one you pointed out would be a great example of how to use iul for purposes other than custom component creation... yeah, me, too. ^_-    --- quote start ---  originally posted by kenland@aug 3 2004, 10:16 pm i&#39;m the master of dummy loads.  that&#39;s about all i&#39;ve learned to do.  the real stuff i have to rely on you hw types.  --- quote end ---   i&#39;m not much of a type of anything. i&#39;ve done everything from pcb layout to board assembly to dsp to object-oriented design, so the whole hw guys vs. sw guys thing looks pretty silly to me. i&#39;m a big believer in cross-training.  <!--quotebegin-kenland@Aug 3 2004, 10:16 PM but i think an example that would excercise your port would be a great addition to get people up and running quickly.  just because i&#39;ve wasted a few months attempting this doesn&#39;t mean others should have to.  http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/smile.gif   --- Quote End ---   The thing is, there&#39;s lots of things you can do to exercise a FIFO port; most of them are pretty trivial to implement. The simplest thing is, of course, create a FIFO and two FIFO Interfaces, one read and one write; hook them up and beat on them.  I&#39;ll be testing things in my environs, but it won&#39;t be exhaustive; hence, the 0.1 version number. I have looked at the generated Verilog, and it looks right, so I&#39;m pretty confident. But if you have a better idea, or if there&#39;s something obvious I&#39;m missing, please say so.