Hi mates!I have a question about when it is necesary to re-generate my niosII system. I am writting my own component to connect it through Avalon to the uP NiosII. Every time I change the verilog/vhdl code is it necesary to re-generate the sopc-system? It is supposed that the changes in the code don't affect to the component interfaces. Many thanks.
If there are no changes in top signals (e.g. new signals, signal removal, width change, etc), then the SOPC system can be left as it is, but You have to resynthesize the code.