remote update IP with cyclone10 LP

[NZami]

Hi,

I used the remote update core to load 2 images (factory and application) with cyclone III work with Active parallel mode. Now I try to load the 2 images to cyclone10 LP. I work now at Active Serial mode and S25FL128M flash.

there are some question I want to ask:

1. Dose the Remote Update IP work at cyclone10 LP?
2. The remote update core at cyclone III add 22 bits data_in bus and now I have 24 bits, how I load the start address of the application image 0x200000?
3. I generate jic file with 2 sof file (at 2 different pages) but only the factory image is loaded (page 0, start address 0x00), what could be the reason?

I enabled the REMOTE configuration option at quartus.

I working with Quartus Prime Lite 18.1

Niv.

[Nooraini_Y_Intel]

Hi NZami,

The Cyclone 10 LP only support Remote System Update in Active Serial mode. You can refer to the existing Cyclone 10 LP Remote System Upgrade Design Example User Guide in the link below:

https://fpgawiki.intel.com/uploads/9/93/C10LP_RSU_Example_UG_170_v1.pdf

The example design can be found from the link below:

https://fpgacloud.intel.com/devstore/platform/17.0.0/Standard/cyclone-10-lp-remote-system-update-design-example/

Application image boot address to be written to the Remote Update IP is obtained by truncating 2 LSB bits from the start address. The example below shows truncating 2 LSB bits from 0x200000h which results in 0x080000h.

0010 0000 0000 0000 0000 0000 --> 0000 1000 0000 0000 0000 0000

Then , in the Convert Programming File utilities, when setting the Application image start address, you need to set to 0x20000h.

Regards,

Nooraini

[NZami]

Thanks for the answer. I need to understand the adress I put at the converting program. Is it 200000h or 20000h? Niv. בתאריך 2 בינו׳ 2019 13:31,‏ Intel Forums <supportreplies@intel.com> כתב: Hi NZami, The Cyclone 10 LP only support Remote System Update in Active Serial mode. You can refer to the existing Cyclone 10 LP Remote System Upgrade Design Example User Guide in the link below: https://fpgawiki.intel.com/uploads/9/93/C10LP_RSU_Example_UG_170_v1.pdf The example design can be found from the link below: https://fpgacloud.intel.com/devstore/platform/17.0.0/Standard/cyclone-10-lp-remote-system-update-design-example/ Application image boot address to be written to the Remote Update IP is obtained by truncating 2 LSB bits from the start address. The example below shows truncating 2 LSB bits from 0x200000h which results in 0x080000h. 0010 0000 0000 0000 0000 0000 --> 0000 1000 0000 0000 0000 0000 Then , in the Convert Programming File utilities, when setting the Application image start address, you need to set to 0x20000h. Regards, Nooraini [https://forums.intel.com/img/userprofile/default_profile_45_v2.png?fromEmail=1]<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0050P000008ASID-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1546428816545&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> NYusof<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0050P000008ASID-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1546428816545&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> (Intel) Hi NZami, The Cyclone 10 LP only support Remote System Update in Active Serial mode. You can refer to the existing Cyclone 10 LP Remote System Upgrade Design Example User Guide in the link below: https://fpgawiki.intel.com/uploads/9/93/C10LP_RSU_Example_UG_170_v1.pdf<https://urldefense.proofpoint.com/v2/url?u=https-3A__fpgawiki.intel.com_uploads_9_93_C10LP-5FRSU-5FExample-5FUG-5F170-5Fv1.pdf&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXrJ60&m=mcrgEubXkDPbsU7gBiwvYyrCO1oOD6XqbUF-uv9lEzQ&s=e21jTDDulNUuVH6zV-mOCpAdPwz7wddWpNPbgBAX4co&e=> The example design can be found from the link below: https://fpgacloud.intel.com/devstore/platform/17.0.0/Standard/cyclone-10-lp-remote-system-update-design-example/<https://urldefense.proofpoint.com/v2/url?u=https-3A__fpgacloud.intel.com_devstore_platform_17.0.0_Standard_cyclone-2D10-2Dlp-2Dremote-2Dsystem-2Dupdate-2Ddesign-2Dexample_&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXrJ60&m=mcrgEubXkDPbsU7gBiwvYyrCO1oOD6XqbUF-uv9lEzQ&s=ZmHK5L_cuMOzbwcJRRu70U2J7ZSBT...> Application image boot address to be written to the Remote Update IP is obtained by truncating 2 LSB bits from the start address. The example below shows truncating 2 LSB bits from 0x200000h which results in 0x080000h. 0010 0000 0000 0000 0000 0000 --> 0000 1000 0000 0000 0000 0000 Then , in the Convert Programming File utilities, when setting the Application image start address, you need to set to 0x20000h. Regards, Nooraini View/Answer<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0D70P000006AiRp-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1546428816545&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> or reply to this email Replying to [https://forums.intel.com/img/userprofile/default_profile_45_v2.png?fromEmail=1]<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0050P000008JVDy-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1546428816545&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> NZami<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0050P000008JVDy-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1546428816545&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> (Customer) asked a question. Tuesday, 1 January 2019 17:08<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0D50P00004ATpUf-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1546428816545-26OpenCommentForEdit-3D1&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh0...> remote update IP with cyclone10 LP Hi, I used the remote update core to load 2 images (factory and application) with cyclone III work with Active parallel mode. Now I try to load the 2 images to cyclone10 LP. I work now at Active Serial mode and S25FL128M flash. there are some question I want to ask: 1. Dose the Remote Update IP work at cyclone10 LP? 2. The remote update core at cyclone III add 22 bits data_in bus and now I have 24 bits, how I load the start address of the application image 0x200000? 3. I generate jic file with 2 sof file (at 2 different pages) but only the factory image is loaded (page 0, start address 0x00), what could be the reason? I enabled the REMOTE configuration option at quartus. I working with Quartus Prime Lite 18.1 Niv. [https://forums.intel.com/img/userprofile/default_profile_45_v2.png?fromEmail=1]<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0050P000008ASID-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1546428816545&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> NYusof<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0050P000008ASID-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1546428816545&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> (Intel) Hi NZami, The Cyclone 10 LP only support Remote System Update in Active Serial mode. You can refer to the existing Cyclone 10 LP Remote System Upgrade Design Example User Guide in the link below: https://fpgawiki.intel.com/uploads/9/93/C10LP_RSU_Example_UG_170_v1.pdf<https://urldefense.proofpoint.com/v2/url?u=https-3A__fpgawiki.intel.com_uploads_9_93_C10LP-5FRSU-5FExample-5FUG-5F170-5Fv1.pdf&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXrJ60&m=mcrgEubXkDPbsU7gBiwvYyrCO1oOD6XqbUF-uv9lEzQ&s=e21jTDDulNUuVH6zV-mOCpAdPwz7wddWpNPbgBAX4co&e=> The example design can be found from the link below: https://fpgacloud.intel.com/devstore/platform/17.0.0/Standard/cyclone-10-lp-remote-system-update-design-example/<https://urldefense.proofpoint.com/v2/url?u=https-3A__fpgacloud.intel.com_devstore_platform_17.0.0_Standard_cyclone-2D10-2Dlp-2Dremote-2Dsystem-2Dupdate-2Ddesign-2Dexample_&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXrJ60&m=mcrgEubXkDPbsU7gBiwvYyrCO1oOD6XqbUF-uv9lEzQ&s=ZmHK5L_cuMOzbwcJRRu70U2J7ZSBT...> Application image boot address to be written to the Remote Update IP is obtained by truncating 2 LSB bits from the start address. The example below shows truncating 2 LSB bits from 0x200000h which results in 0x080000h. 0010 0000 0000 0000 0000 0000 --> 0000 1000 0000 0000 0000 0000 Then , in the Convert Programming File utilities, when setting the Application image start address, you need to set to 0x20000h. Regards, Nooraini Wednesday, 2 January 2019 13:32<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0D70P000006AiRp-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1546428816545&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> You're receiving emails when someone "Comments on my posts." To change or turn off Forums email, log in<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_-5Fui_core_feeds_notification_ChatterEmailSettings-3Fsetupid-3DCollaborationEmailSettings-26fromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1546428816545&d=DwMFaQ&c=euGZstcaTDll...

[Nooraini_Y_Intel]

Hi NZami,

It was a typo error. In the Convert Programming File utilities, when setting the Application image start address, you need to set to 0x200000h.

I suggest that you can look into the existing example design which should provide the information that you need.

Regards,

Nooraini

[NZami]

I look at the example and in the example I don’t see the truncation of the 2 LSB from the address. Do I need to truncate the 2 LSB? Regards Niv.

[Nooraini_Y_Intel]

Hi NZami,

I further checked, it seems for newer Quartus version in the remote update IP, you don't need to truncate 2 LSB of the start address. This should be taken care by the remote update IP. For active serial devices using the 24-bit addressing, such as EPCS128/EPCQ128 and lower density, the boot_address[23..2] corresponds to the upper 22 bits of the 24-bits boot address while the boot_address[1..0] is read as 2'b0. Thus you can set the application image start address value 0x200000 to data_in[23..0] of the remote update IP.

Regards,

Nooraini

[NZami]

Thanks for your answer, It's working well now. I have one more question. Can I use .rbf file to reconfigure the application image in the flash when I work with serial flash (Active Serial mode)? Thanks Niv.

[Nooraini_Y_Intel]

Hi NZami,

Instead of using .rbf file, you need to use the .rpd file for ASx1/x4 configuration scheme. AS configuration scheme support .jic, .pof and .rpd file format. The .rpd file is a binary file for EPCQ/EPCS/EPCQA devices containing a binary bitstream of configuration data for FPGAs that support Active Serial configuration. The .rbf file is not supported in AS mode as there are option bits for AS mode is not available in the .rbf file. This has been explained from the following KDB:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd05182010_4.html

In version 13.1 and later of the Quartus® II software, you can generate a .rpd file which only contains the required configuration data according to the following steps below:

1.     Open the File -> Convert Programming Files GUI.

2.     Select Programming file type: Programmer Object File (.pof) or JTAG Indirect Configuration file (.jic).

3.     Select the appropriate configuration device and Mode.

4.     Click SOF Data in the window at the bottom then Add File and add the SRAM Object file (.sof).

5.     Check the Create config data RPD box.

6.     Click Generate.

Regards,

Nooraini

[NZami]

I Yusof, I generate rpd file at the way you mention. I write the rpd file to the configuration flash to the application image address. After i power up the FPGA again the FPGA come with the boot image because the application image is not valid. What could be the reason? Should I copy the rpd file as is to the configuration flash? Is there anything special for generate only application image rpd (start from address 0x200000)? Niv. בתאריך 10 בינו׳ 2019 9:43,‏ Intel Forums <supportreplies@intel.com> כתב: Hi NZami, Instead of using .rbf file, you need to use the .rpd file for ASx1/x4 configuration scheme. AS configuration scheme support .jic, .pof and .rpd file format. The .rpd file is a binary file for EPCQ/EPCS/EPCQA devices containing a binary bitstream of configuration data for FPGAs that support Active Serial configuration. The .rbf file is not supported in AS mode as there are option bits for AS mode is not available in the .rbf file. This has been explained from the following KDB: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd05182010_4.html In version 13.1 and later of the Quartus® II software, you can generate a .rpd file which only contains the required configuration data according to the following steps below: 1. Open the File -> Convert Programming Files GUI. 2. Select Programming file type: Programmer Object File (.pof) or JTAG Indirect Configuration file (.jic). 3. Select the appropriate configuration device and Mode. 4. Click SOF Data in the window at the bottom then Add File and add the SRAM Object file (.sof). 5. Check the Create config data RPD box. 6. Click Generate. Regards, Nooraini [https://forums.intel.com/img/userprofile/default_profile_45_v2.png?fromEmail=1]<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0050P000008ASID-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1547106359040&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> NYusof<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0050P000008ASID-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1547106359040&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> (Intel) Hi NZami, Instead of using .rbf file, you need to use the .rpd file for ASx1/x4 configuration scheme. AS configuration scheme support .jic, .pof and .rpd file format. The .rpd file is a binary file for EPCQ/EPCS/EPCQA devices containing a binary bitstream of configuration data for FPGAs that support Active Serial configuration. The .rbf file is not supported in AS mode as there are option bits for AS mode is not available in the .rbf file. This has been explained from the following KDB: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd05182010_4.html<https://urldefense.proofpoint.com/v2/url?u=https-3A__www.intel.com_content_www_us_en_programmable_support_support-2Dresources_knowledge-2Dbase_solutions_rd05182010-5F4.html&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXrJ60&m=uKphs5PzF-jKn7VHNJvA44SNY12EU4cvNJ0ym4YD59E&s=0qvUBFfq1Ox_iV4qmCMzfrQBfT3I...> In version 13.1 and later of the Quartus® II software, you can generate a .rpd file which only contains the required configuration data according to the following steps below: 1. Open the File -> Convert Programming Files GUI. 2. Select Programming file type: Programmer Object File (.pof) or JTAG Indirect Configuration file (.jic). 3. Select the appropriate configuration device and Mode. 4. Click SOF Data in the window at the bottom then Add File and add the SRAM Object file (.sof). 5. Check the Create config data RPD box. 6. Click Generate. Regards, Nooraini View/Answer<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0D70P000006BCER-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1547106359040&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> or reply to this email Replying to [https://forums.intel.com/img/userprofile/default_profile_45_v2.png?fromEmail=1]<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0050P000008JVDy-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1547106359040&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> NZami<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0050P000008JVDy-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1547106359040&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> (Customer) asked a question. Tuesday, 1 January 2019 17:08<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0D50P00004ATpUf-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1547106359040-26OpenCommentForEdit-3D1&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh0...> remote update IP with cyclone10 LP Hi, I used the remote update core to load 2 images (factory and application) with cyclone III work with Active parallel mode. Now I try to load the 2 images to cyclone10 LP. I work now at Active Serial mode and S25FL128M flash. there are some question I want to ask: 1. Dose the Remote Update IP work at cyclone10 LP? 2. The remote update core at cyclone III add 22 bits data_in bus and now I have 24 bits, how I load the start address of the application image 0x200000? 3. I generate jic file with 2 sof file (at 2 different pages) but only the factory image is loaded (page 0, start address 0x00), what could be the reason? I enabled the REMOTE configuration option at quartus. I working with Quartus Prime Lite 18.1 Niv. [https://forums.intel.com/img/userprofile/default_profile_45_v2.png?fromEmail=1]<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0050P000008ASID-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1547106359040&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> NYusof<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0050P000008ASID-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3D1547106359040&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXr...> (Intel) Hi NZami, Instead of using .rbf file, you need to use the .rpd file for ASx1/x4 configuration scheme. AS configuration scheme support .jic, .pof and .rpd file format. The .rpd file is a binary file for EPCQ/EPCS/EPCQA devices containing a binary bitstream of configuration data for FPGAs that support Active Serial configuration. The .rbf file is not supported in AS mode as there are option bits for AS mode is not available in the .rbf file. This has been explained from the following KDB: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd05182010_4.html<https://urldefense.proofpoint.com/v2/url?u=https-3A__www.intel.com_content_www_us_en_programmable_support_support-2Dresources_knowledge-2Dbase_solutions_rd05182010-5F4.html&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=6wL4d6ccMT80jh02goqOtZZt2NCC5Ff_LtTm9SXrJ60&m=uKphs5PzF-jKn7VHNJvA44SNY12EU4cvNJ0ym4YD59E&s=0qvUBFfq1Ox_iV4qmCMzfrQBfT3I...> In version 13.1 and later of the Quartus® II software, you can generate a .rpd file which only contains the required configuration data according to the following steps below: 1. Open the File -> Convert Programming Files GUI. 2. Select Programming file type: Programmer Object File (.pof) or JTAG Indirect Configuration file (.jic). 3. Select the appropriate configuration device and Mode. 4. Click SOF Data in the window at the bottom then Add File and add the SRAM Object file (.sof). 5. Check the Create config data RPD box. 6. Click Generate. Regards, Nooraini Thursday, 10 January 2019 09:45<https://urldefense.proofpoint.com/v2/url?u=https-3A__forums.intel.com_0D70P000006BCER-3FfromEmail-3D1-26s1oid-3D00DU0000000YT3c-26s1nid-3D0DB0P000000U1Hq-26s1uid-3D0050P000008JVDy-26s1ext-3D0-26emkind-3DchatterCommentNotification-26emtm-3

[Nooraini_Y_Intel]

Hi NZami,

What is the reconfiguration trigger condition value that you have read back during factory image? Since the FPGA gets revert back into the factory image then you should be able to read back the reconfiguration trigger condition value. You need to set the param[] = 111, read_source[]=01 and trigger the read_param signal. Then when the busy signal is low monitor the data_out[] for the reconfiguration trigger condition value. You can use Signal Tap to monitor these signals.

How did you write the .rpf file into the flash device? The default generated .rpd file from Quartus tools is little endian format. By default the programming the .jic/pof file, the Quartus programmer will perform the bit swapping (LSb first) before writing the data into the EPCS/EPCQ/EPCQA device. Thus you need to perform the bit swapping when using the little endian .rpd file before writing the data into EPCS/EPCQ/ECPQA device. If you set the big endian option in the Convert Programming tools when generation the .rpd file, then you don’t require to perform the bit swapping since the generated .rpd file is in big endian format. 

Regards,

Nooraini 

[NZami]

Thanks Yusof for your help. Now it's work the problem was the bits swapping.