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resetrequest and restart

Altera_Forum
Honored Contributor II
833 Views

Hi, 

 

i have a SPOC-System with 3 NIOS II Processors. One of the processors is used to download software to the others. 

For download i set the resetrequst signal to the cpu and then i wait until the resettaken is asserted. Then i download the hex-file to the memory and release resetrequest. This works fine. 

But when i only restart a processor by setting the resetrequest, waiting for resettaken and resetting resetrequest the processor does not start again. It only works, when i download the hex-file before releasing the resetrequest. 

Do i have to clear the stack or something before resetting the resetrequest? 

 

Thanks, Paddy
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4 Replies
Altera_Forum
Honored Contributor II
101 Views

Works for us. 

We did have to implement a latch on 'resettaken' - since IIRC that is asserted for one clock each time around the reset loop. 

 

ISTR that, while reset, the cpu loops reading the first instruction from memory, then checks resetrequest and decides not to execute it. 

So checking for resettaken going away is slightly tricky.
Altera_Forum
Honored Contributor II
101 Views

I have implemented a latch for checking resetrequest. The CPU always starts after resetrequest is released, when i do the following: 

 

Step1: assert resetrequest 

Step2: wait for a rising edge on resettaken 

Step3: download hex 

Step4: deassert resetrequest 

 

but if i do not download the hex-file (Step 3) the CPU does not start again. 

Thats why i thougt, that i have to do something with the RAM (Stack reset or smthg.) before releasing resetrequest. 

 

Thanks, Paddy
Altera_Forum
Honored Contributor II
101 Views

Possibly the cpu has locked up somewhere (maybe waiting for some avalon slave) because it executed garbage instructions? 

It might be worth planting a 'br .' (0xfffc << 6 | 6) at the reset instruction before the download.
Altera_Forum
Honored Contributor II
101 Views

Thanks for your reply! 

 

I thought that the resetrequest executes the reset after finishing the last avalon instruction !?! Could it be that a avalon slave is blocked, because the CPU resets?
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