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12409 Discussions

sdram use different clk with other ip in nios

Honored Contributor II

Hi everyone: 


I am new to altera and nios. 

Recently I download a reference design from internet, it use sdram as code memory, and it add a sdram controller. 

I find that the sdram controller use 100Mhz clk and the other ip (including the Nios II processor) use 50Mhz clk. 

Will the sdram controller automatically recognize the settings and make the exchange of data and instructions between the Nios II Processor and adram? 



if i use sdram as code memory, can it be shared by other ip, or use as data memory for the system? assume the sdram is big enough to stroage the code.
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3 Replies
Honored Contributor II


Qsys automatically inserts a generic clock crossing bridge between devices operated at different clock frequency. For improved performance you may want to add an explicit clock crossing bridge component and configure it according to your needs. 

Anyway, I believe in your case the frequency splitting is not strictly necessary. What device are you targeting? Cyclone III and later devices can easily run a Nios system at 100MHz, so you'd rather setup everything for this frequency and avoid the delays and latencies involved with crossing clock domains. 

The conservative 50MHz is typical in reference designs: it helps you to easily meet timing constraints, at the expense of performance. 



The answer is definitely Yes
Honored Contributor II

hi cri72 


about the question2, can you give me more details or a document? 

thanks a lot!
Honored Contributor II

If your sdram controller exposes a MM slave interface, there's no difference between sdram or any other type of memory. From Nios point of view (or any other MM bus master), sdram is equivalent to onchip ram, flash memory, sram or whatever. Clearly you'll have different access times, but you usually don't bother it at the Nios code level. 

Placing both code and data in sdram is indeed the common practice. 

You can have N memory devices connected to Nios and you can distribute code/data sections across them. 

For example you map generic code and data to sdram, but you can move time critical functions to faster onchip ram to optimize performance. You can remap whole code sections by adjusting linker settings. 

You can also remap a single function or variable by using the attribute directive: 

__attribute__ ((section (<memory device name>))); 


Regarding the possibility of sharing sdram among different ip, the answer is still Yes. 

The typical situation is when you have Nios processor and one or more DMA devices connected to sdram (or, in general, to the data bus). Both are MM masters and they can independently read/write the same memory device. 

Bus arbitration is managed automatically by the Avalon bus fabric; you only have to worry about the consistency of the r/w operations (i.e. the dma write must not corrupt Nios code, but it should write in the assigned memory area which is supposed to store data).  

This also applies when you have multiple Nios processors and a single sdram memory: each processor would run code from a specific sdram address range and they could possibly share a common address range for exchanging some data. 


Browse the Nios and sopc information for extended info and examples: