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sdram write/read in arria ii gx dev. board

Altera_Forum
Honored Contributor II
829 Views

Hi 

 

I am trying to write and read the DDR3 SDRAM on my Arria II Gx Dev. board with the following code. 

 

# include <stdio.h> # include "system.h" # include "altera_avalon_pio_regs.h" # include "alt_types.h" int main() { // test message printf("Hello from Nios II!\n"); // ========== // test SDRAM // ========== // write SDRAM int i = 0; for(i = 0; i < 32; i++) { *((alt_32*)ALTMEMDDR_0_BASE + i) = (alt_32)i; } // read SDRAM for(i = 0; i < 32; i++) { alt_32 data = *((alt_32*)ALTMEMDDR_0_BASE + i); printf("SDRAM = %d\n", i, data); } // flash led every one second while(1) { IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0xf); usleep(1000000); IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x0); usleep(1000000); } return 0; }  

 

Basically, I write 0,1,2,3,...,31 to the DDR3 SDRAM and read these data back for testing. 

However, when those read data are displayed in the console using printf function, some of the access fails, as you can see in the following: 

 

Hello from Nios II! SDRAM = 0 SDRAM = 0 SDRAM = 0 SDRAM = 0 SDRAM = -1 SDRAM = -1 SDRAM = -1 SDRAM = -1 SDRAM = 0 SDRAM = 0 SDRAM = -1 SDRAM = 0 SDRAM = 0 SDRAM = 0 SDRAM = 14 SDRAM = 15 SDRAM = 16 SDRAM = 17 SDRAM = 18 SDRAM = 19 SDRAM = 20 SDRAM = 21 SDRAM = 22 SDRAM = 23 SDRAM = 24 SDRAM = 25 SDRAM = 26 SDRAM = 27 SDRAM = 28 SDRAM = 29 SDRAM = 30 SDRAM = 31  

 

When I run my program again, the result is always different. 

For example: some of data in SDRAM[14:31] may be wrong this time but other data may be correct. 

Does any one have any clue on this problem??? 

Thanks a lot. 

(I also provide my qsys design as an attached image if anyone thinks the problem may come from my qsys design)
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3 Replies
Altera_Forum
Honored Contributor II
112 Views

Do you have the data cache enabled? 

It might be making things more confusing.
Altera_Forum
Honored Contributor II
112 Views

Hi dsl 

 

Thank you for the reply. 

 

I'm using NIOS II/s as my cpu. 

I think the data cache should be disabled by default. 

In the "system.h", I also find "#define NIOS2_DCACHE_SIZE 0" 

 

I try to use IOWR and IORD to access the memory instead of using the pointer, because another post in this forum mentioned that the pointer access can use the data cache. 

The problem is still the same.
Altera_Forum
Honored Contributor II
112 Views

I check some documents about SDRAM design again and run a tcl file which is about board trace model. The tcl file named "ArriaIIGX_DDR3_BTModels.tcl" can be found in some reference designs from Altera. 

 

Now, I get half chance to read those 32 data from SDRAM successfully. 

In failed cases, most the data read from SDRAM are correct. 

 

I'm wondering if the timing issue is the root cause of my problem, because I guess the board trace model helps my design to have a better performance in timing. 

 

Thanks.
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