Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12409 Discussions

sg-dma from altera wiki example design on nios

Altera_Forum
Honored Contributor II
1,048 Views

Hello  

 

I used the sg dma example design from  

http://www.alterawiki.com/wiki/file:sg-dma.zip 

 

I run that on arriaV 

 

the qsys connection are as the following 

ram -> tx sgdma -> fifo st -> rx sgdma -> ram 

 

the design is waiting for and "blocked here" 

while(tx_done == 0) {} 

 

 

Can you help how to debug ?  

 

Thanks!
0 Kudos
0 Replies
Reply