Hello
I used the sg dma example design from
http://www.alterawiki.com/wiki/file:sg-dma.zip I run that on arriaV
the qsys connection are as the following
ram -> tx sgdma -> fifo st -> rx sgdma -> ram
the design is waiting for and "blocked here"
while(tx_done == 0) {}
Can you help how to debug ?
Thanks!
