Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,484 Views

soc_system_board_info.xml/hps_common_board_info.xml common accross most devboards ?

I'm using De0-nano-soc & De1-soc from Terasic .. 

neither has soc_system_board_info.xml & hps_common_board_info.xml included in the packages that arrived  

 

& Terasic is claiming their linux sources are proprietary (?? maybe i'll sic the EFF on them ..)  

 

 

so I've been using cv_soc_devkit_ghrd version  

is this going to be 'mostly ok' ?? has anyone fine tuned these files for these boards ?  

 

 

 

having pains trying to get a compile of linux complete&running but that is a post for another thread ...
0 Kudos
13 Replies
Altera_Forum
Honored Contributor I
147 Views

partially functional -- now stuck at loading kernel .... 

just more digging involved ....
Altera_Forum
Honored Contributor I
147 Views

Hey Ralph, 

 

I'm interested in hearing how you go with this board. I have the DE0-nano-SoC and the Arrow SoCkit (which is also a Terasic board). I'm interested in understanding how to build everything from source, i.e, downloading source code from a git repo while not having to hack the source for these particular boards. I also noticed that the DE-nano-SoC code was not easily available and the documents were pretty vague with respect to building the SoC system and Linux code. I figured I'd start with the SoCKit, and then go back to the DE0-nano-SoC once I was familiar with the tool flows. 

 

I haven't had a chance to dive into the HPS side of things yet, I started on the FPGA-side, since I was comfortable there :) 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
147 Views

Hey Dave, 

Yes, started with the FPGA side a while back (was going to be De0-Nano (Cyclone4) with a external CPU (BeagleBoard))  

but flipped over the the De0-Nano-SoC due to space/timing & ram issues  

-- so 95% of my fpga work is done -- mostly have to worry about Fpga2sdram interface 

 

really are living in minimal documentation land here ... (or there is too much & difficult to filter ...) 

 

... with any luck - be booting soon... (tonight ??!?) 

hiho  

R
Altera_Forum
Honored Contributor I
147 Views

 

--- Quote Start ---  

 

really are living in minimal documentation land here ... (or there is too much & difficult to filter ...) 

 

--- Quote End ---  

 

Yes, I've found there to be a lot of documentation, but most of it is not well written. 

 

For example, "How do you create pin assignments for the HPS pins?" would be an obvious question to someone familiar with FPGAs. Its not obvious that the HPS pin assignments are a result of pin settings in the component instance (and are configured by the preloader). I'm not sure whether I have ever seen it stated in an Altera doc, I think I made that realization while watching a tutorial. 

 

 

--- Quote Start ---  

 

... with any luck - be booting soon... (tonight ??!?) 

 

--- Quote End ---  

 

Good luck! 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
147 Views

update : booting . but not really  

or i should say not completely on my own //  

 

i can create all it parts kernel/zImage/rootfs / boot.scr, soc_system.rbf, preloader-mkpimage.bin  

 

but it only boots if i use the socfpga.dtb from the sdcard that came with it (posted on the terasic site) .. .  

 

i have followed suggestions / remove second WDT, drop/disable peripherals in the soc_system.sopcinfo  

i have converted / modified/ loaded generated dts files 

 

 

i have unconverted the working blob to text& re'blob'ed it .. & it still boots  

 

/ all others hang at "loading kernel ...." 

 

I've requested any board*info.xml from Terasic -- they do provide a version for the De1-SOC  

so it should not be a stretch for them to pass it on ---  

 

obviously  

the original device tree does me no good 

it does not support the peripherals i've created  

 

feeling some what stymied
Altera_Forum
Honored Contributor I
147 Views

update Board --> soc_system_board_info.xml<-- for DE0-Nano-Soc can be found in the Workshop images  

http://rocketboards.org/foswiki/view/documentation/socswworkshopseriessdcardimages 

(haven't tried them yet)
Altera_Forum
Honored Contributor I
147 Views

from the files above IT WORKS ---- though note : 

------------ 

sopc2dts has order effects - the first(given in the workshop material) does NOT work  

------------ 

sopc2dts --input soc_system.sopcinfo 

--output soc_system.dts 

--type dts 

--board board_info_DE0_NANO_SOC.xml 

--board hps_common_board_info.xml 

--bridge-removal all 

--clocks 

--------- 

swapping hps_common_board_info.xml & board_info_DE0_NANO_SOC.xml does work :  

--------- 

sopc2dts --input soc_system.sopcinfo 

--output soc_system.dts 

--type dts 

--board hps_common_board_info.xml 

--board board_info_DE0_NANO_SOC.xml 

--bridge-removal all 

--clocks 

----
Altera_Forum
Honored Contributor I
147 Views

 

--- Quote Start ---  

 

from the files above IT WORKS 

 

--- Quote End ---  

 

How much of it works? i.e., do you get to a Linux prompt now with just a console interface, or do you have the console, ethernet, etc working? 

 

I haven't had a chance to play with the board this week. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
147 Views

yes- console, ethernet, mini webserver & fpga is loaded at boot via boot loader (MEL="00000") 

leds are functional (built my code into the HPS_CONTROL_FPGA_LED demo project ) 

 

rebuilt kernel with kernel debug on (so i know its mine)  

the angstrom distribution socfpga_cyclone5 ttys0 

angstrom v2013.12 - kernel 3.10.31-ltsi-05035-g801a40f 

----- 

 

BTW: another interesting hoop to jump through to get good header files  

 

sopcinfo2swinfo soc_system.sopcinfo 

swinfo2header --swinfo soc_system.swinfo 

 

creates amongst others --> hps_0.h <-- which has nice formatted info for the fpga devces ...
Altera_Forum
Honored Contributor I
147 Views

Nice work! 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
147 Views

 

--- Quote Start ---  

Hey Dave, 

-- mostly have to worry about Fpga2sdram interface 

--- Quote End ---  

 

 

Ralph- 

 

Any luck getting the FPGA2SDRAM interface running? I found a bug in how sopcinfo files are processed from Qsys that I've reported to Altera, but I haven't been able to get it working unless there are significant preloader changes required. I'd love to know if I'm missing something simple.
Altera_Forum
Honored Contributor I
147 Views

 

--- Quote Start ---  

Ralph- 

 

Any luck getting the FPGA2SDRAM interface running? I found a bug in how sopcinfo files are processed from Qsys that I've reported to Altera, but I haven't been able to get it working unless there are significant preloader changes required. I'd love to know if I'm missing something simple. 

--- Quote End ---  

 

 

I've had to take a (3 month) break from that section of my code (family stuff ) back into it shortly // 

currently working through MY modifications of the WS3DevelopingDriversForAlteraSoCLinux code to understand a bit better & to get my head back into that space  

spare time is at bit of a premium these days ...
Altera_Forum
Honored Contributor I
147 Views

 

--- Quote Start ---  

I've had to take a (3 month) break from that section of my code (family stuff ) back into it shortly // 

currently working through MY modifications of the WS3DevelopingDriversForAlteraSoCLinux code to understand a bit better & to get my head back into that space  

spare time is at bit of a premium these days ... 

--- Quote End ---  

 

 

I know that feeling...instead of debugging the interface we switched to using an on-chip FIFO until we have a week or so of time for debugging. Good luck!
Reply