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12453 Discussions

system ID and system timestamp not found

Altera_Forum
Honored Contributor II
2,368 Views

Hi, I am facing problem in downloading Nios2 project into the hardware. The program indicate that system ID and system timestamp are not found on target at base address. The system ID properties shows: 

 

System ID base address: 0x9040 

Expected system ID: 0x35a2a5b3 

Actual system ID: N/A 

Expected system timestamp: 1267541979 

Actual system timestamp: N/A 

 

I have loaded nios2_time_limited.sof (my project .sof file) using Quartus II programmer and leave it on before trying to run the nios II on the hardware.  

 

The device family has been set to Cyclone II. The board i using is DE1 board. The switch on the DE1 board is set to 'run'. 

 

I tried to ignore system ID and system timestamp mismatch, the loading of nios II run half way and shows error: 

 

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 

Pausing target processor: not responding. 

Resetting and trying again: FAILED 

Leaving target processor paused 

 

Can any1 help me with this problem? I have search the forum but none of the solution is working for me.
0 Kudos
19 Replies
Altera_Forum
Honored Contributor II
332 Views

Try to delete the Run Configuration and recreate a new Run Configuration.

Altera_Forum
Honored Contributor II
332 Views

I have tried create a new run config but it does not work. I might have overlook some procedure while loading Nio2 2 into DE1...can someone with experience of using Nios 2 and DE1 provide me with important steps to download nios 2 into DE1?  

 

Btw...is it correct to set the switch to RUN instead of PROG when loading Nios 2? And do I need to connect AC supply while programming Nios 2? I'm currently using voltage supply from USB. 

 

I'm also getting "Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details" 

 

In the Ignored Timing Assignments: 

 

Cut Timing Path On * data_in_d1 nios_reset_clk_0_domain_synch_module No timing path applicable to specified source and destination 

Cut Timing Path On * data_in_d1 nios_reset_clk_0_domain_synch_module  

 

Is this timing assignment issue the cause of my problem?
Altera_Forum
Honored Contributor II
332 Views

http://www.nioswiki.com/embedded_systems_lab 

The lab files here would show how to download and run software in DE1 

Yes , the AC supply needs to be connected.
Altera_Forum
Honored Contributor II
332 Views

Thanks very much. The link is very helpful for me :p

Altera_Forum
Honored Contributor II
332 Views

Hi 

 

I am facing the same problem while adding my own component. I am using DE2 board. Can you suggest me the solution? 

 

Mumble
Altera_Forum
Honored Contributor II
332 Views

Hi, is the Nios II working fine before adding those components? 

 

Some of the steps i usually do after modify SOPC Builder are making sure that i load 'xxx_time_limited.sof' instead of 'xxx.pof'; right click 'xxx_bsp'(in Nios II project workspace)->Nios II->BSP Editor->Linker Script and restore default to the both Region Name and Section Name; and click 'Generate BSP' in the same menu as 'BSP Editor'.
Altera_Forum
Honored Contributor II
332 Views

I never got option to load .pof file. I always use .sof. 

 

I can't see 'xxx_time_limited.sof' file in my project folder.  

 

Kindly suggest. 

 

Mumble
Altera_Forum
Honored Contributor II
332 Views

xxx is the project name. For example, my project name is nios, the .sof file will be nios_time_limited.sof.

Altera_Forum
Honored Contributor II
332 Views

I can't see any XXX_time_limited.sof file in my project folder. I do have XXX.sof file which I download on target board.

Altera_Forum
Honored Contributor II
332 Views

Maybe our version is different? I am using Quartus II 9.1 web edition.

Altera_Forum
Honored Contributor II
332 Views

Hi, 

 

I rebuilt my whole design again and it is not giving the mismatch error anymore :) . 

 

Thanks for the help :) 

 

Sonal.
Altera_Forum
Honored Contributor II
332 Views

Hi,how are you!I'm Chinese,I have the same problem with you,I don't know how you have the problem solved even though I read this page,may because of my poor English. Can you help me?

Altera_Forum
Honored Contributor II
332 Views

Thank you ;)

Altera_Forum
Honored Contributor II
332 Views

Hi Guys, 

 

I am having a similar issue, I have a timestamp mismatch and cannot figure out what it is. I have check the sopcinfo file, recompiled my whole design including quartus and cannot resolve it. 

 

Can anyone help?
Altera_Forum
Honored Contributor II
332 Views

Generally, sysid ip core should be added in your SOPC system, and rename it sysid.sysid and timestamp are updated at every generation in SOPC Builder,then BSP in Nois SBT should be regenerated. 

Before download software file(debug or run in Nois SBT),.sof file must be download to your FPGA.Because when you debug or run program,Nois SBT read sysid and timestamp from the hardware in FPGA.
Altera_Forum
Honored Contributor II
332 Views

我也碰到过非常多的如此问题,一般重新做一个nios就可以了,碰上还不行的就只能重新做sopc核,但是有一次同事说他的怎么都不行,我过去一看,发现quartus没有破解好,因为发现有编译的time-limited.sof文件,后来重新破解编译后,就可以下载了!

Altera_Forum
Honored Contributor II
332 Views

Dear All, 

 

I am facing the same issue. But i have checked all of the trouble shooting points... Kindly let know where i could be going wrong... 

 

I am using Cyc III with NIOS II and Quartus II 12.0 sp1. I have been using it to program and flash using Flash Programmer in NIOS IDE.  

 

Recently i wanted to test some stubs so copied the project to another folder using Project > Copy Project option.  

 

Then after removing all logic and retained only required ones... And doing a JTAG for Quartus and NIOS too... (NIOS - RUN CONFIGURATIONS AS NIOS HARDWARE) 

 

have included sysid and timer in QSYS model. 

 

I follow the steps correctly... 1. Generate QSYS, 2. Compile Quartus II, 3. Generate BSP in NIOS, 4. Copy SOPC file (.sof) using JTAG, 5. then run - "RUN CONFIGURATION" from NIOS IDE. 

 

I keep getting Mismatch in sysid and timestamp. Kindly help.
Altera_Forum
Honored Contributor II
332 Views

 

--- Quote Start ---  

Dear All, 

 

I am facing the same issue. But i have checked all of the trouble shooting points... Kindly let know where i could be going wrong... 

 

I am using Cyc III with NIOS II and Quartus II 12.0 sp1. I have been using it to program and flash using Flash Programmer in NIOS IDE.  

 

Recently i wanted to test some stubs so copied the project to another folder using Project > Copy Project option.  

 

Then after removing all logic and retained only required ones... And doing a JTAG for Quartus and NIOS too... (NIOS - RUN CONFIGURATIONS AS NIOS HARDWARE) 

 

have included sysid and timer in QSYS model. 

 

I follow the steps correctly... 1. Generate QSYS, 2. Compile Quartus II, 3. Generate BSP in NIOS, 4. Copy SOPC file (.sof) using JTAG, 5. then run - "RUN CONFIGURATION" from NIOS IDE. 

 

I keep getting Mismatch in sysid and timestamp. Kindly help. 

--- Quote End ---  

 

 

this problem can caused by many reason.May your project,may your hardware.You can do a simple project with inner ram.之前我碰到过license,硬件的dqm设计不对,和最近的多port DDR中,nios使用的指令缓冲区被其他port破坏。
Altera_Forum
Honored Contributor II
332 Views

I am getting Chinese chars in the post.. not able to understand. Meanwhile my on-chip memory is not sufficient for my testing and am using a SRAM for NIOS code. I have made my Processor reset and exceptio point to On-Chip ram and all other sections of the code in SRAM.

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