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Altera_Forum
Honored Contributor I
793 Views

the "signed" type i/o in vhd file disapear when i try to add my new component

hi every one; 

i write my own component in vhd and try to add it in qsys, 

in the component editor, i and my vhd file and click analyze files, it shows 0 errors and 0 warnings. 

but in the signals & interfaces tab, i can not find the "signed" i/o in vhd files 

like: 

S_encoder1_Z_reg_out : out STD_LOGIC_VECTOR(1 downto 0); 

S_encoder1_AB_for_interpolation_reg_out : out STD_LOGIC_VECTOR(1 downto 0); 

S_encoder1_period_counter_reg_out : out signed(31 downto 0); 

 

the "signed" signal does not appear in signals & interfaces tab, the std_logic and std_logic_vector signals are ok 

 

how can i fix this? 

should i have to change the signed to std_logic_vector?
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3 Replies
Altera_Forum
Honored Contributor I
51 Views

btw: 

i have included the IEEE.NUMERIC_STD in vhd file 

use IEEE.NUMERIC_STD.ALL;
Altera_Forum
Honored Contributor I
51 Views

 

--- Quote Start ---  

hi every one; 

i write my own component in vhd and try to add it in qsys, 

in the component editor, i and my vhd file and click analyze files, it shows 0 errors and 0 warnings. 

but in the signals & interfaces tab, i can not find the "signed" i/o in vhd files 

like: 

S_encoder1_Z_reg_out : out STD_LOGIC_VECTOR(1 downto 0); 

S_encoder1_AB_for_interpolation_reg_out : out STD_LOGIC_VECTOR(1 downto 0); 

S_encoder1_period_counter_reg_out : out signed(31 downto 0); 

 

the "signed" signal does not appear in signals & interfaces tab, the std_logic and std_logic_vector signals are ok 

 

how can i fix this? 

should i have to change the signed to std_logic_vector? 

--- Quote End ---  

 

 

Prefered method to describe external interface for module - std_logic_vector and in implementation you can use casting to or from another type. 

 

Hope this problem not due optimisation when CAD rename or even remove unused ports. 

Perhaps if std_logic_vector works for you then you can use workaround : 

 

entity BlaBlaBla is port ( S_encoder1_period_counter_reg_out : out std_logic_vector (31 downto 0 )); end BlaBlaBla; architecture v of BlaBlaBla is signal S_encoder1_period_counter_reg : signed (31 downto 0 ); begin S_encoder1_period_counter_reg_out <= std_logic_vector(S_encoder1_period_counter_reg); end v;
Altera_Forum
Honored Contributor I
51 Views

Signed/unsigned are perfectly fine for you to use in your HDL design, even at the top level. 

But QSYS is pretty rubbish, and only allows std_logic/std_logic_vector ports: 

 

Answer: dont use QSYS or just do an internal conversion, as alex suggests above.
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