Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

uClinux TSE not working

Altera_Forum
Honored Contributor II
885 Views

Hello, 

 

i have a problem with my Ethernet on the DE2-115 Board using uClinux. 

When i set up "eth0": 

root:/> ifconfig eth0 192.168.14.92 up root:/> ifconfig eth0 eth0 Link encap:Ethernet HWaddr 00:11:22:33:44:55 inet addr:192.168.14.92 Bcast:192.168.14.255 Mask:255.255.255.0 UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:7 errors:7 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 Base address:0x2400  

There are 7 errors on RX-Line. 

 

When i do "ping": 

root:/> ping 192.168.14.14 PING 192.168.14.14 (192.168.14.14): 56 data bytes ^C --- 192.168.14.14 ping statistics --- 3 packets transmitted, 0 packets received, 100% packet loss root:/> ifconfig eth0 eth0 Link encap:Ethernet HWaddr 00:11:22:33:44:55 inet addr:192.168.14.92 Bcast:192.168.14.255 Mask:255.255.255.0 UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:43 errors:43 dropped:0 overruns:0 frame:0 TX packets:3 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 Base address:0x2400  

the Errors increase. 

 

Output of ethtool: 

root:/> ethtool eth0 Settings for eth0: Supported ports: Supported link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Half 1000baseT/Full Supports auto-negotiation: Yes Advertised link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Half 1000baseT/Full Advertised auto-negotiation: Yes Speed: 1000Mb/s Duplex: Full Port: MII PHYAD: 17 Transceiver: external Auto-negotiation: on Current message level: 0x00000000 (0) Link detected: yes  

 

root:/> ethtool -S eth0 NIC statistics: aFramesTransmittedOK: 3 aFramesReceivedOK: 0 aFramesCheckSequenceErrors: 3 aAlignmentErrors: 1 aOctetsTransmittedOK: 138 aOctetsReceivedOK: 0 aTxPAUSEMACCtrlFrames: 0 aRxPAUSEMACCtrlFrames: 0 ifInErrors: 47 ifOutErrors: 0 ifInUcastPkts: 0 ifInMulticastPkts: 0 ifInBroadcastPkts: 0 ifOutDiscards: 0 ifOutUcastPkts: 0 ifOutMulticastPkts: 0 ifOutBroadcastPkts: 3 etherStatsDropEvent: 0 etherStatsOctets: 120993 etherStatsPkts: 47 etherStatsUndersizePkts: 0 etherStatsOversizePkts: 0 etherStatsPkts64Octets: 0 etherStatsPkts65to127Octets: 40 etherStatsPkts128to255Octets: 3 etherStatsPkts256to511Octets: 0 etherStatsPkts512to1023Octets: 0 etherStatsPkts1024to1518Octets: 1 etherStatsPkts1519toXOctets: 0 etherStatsJabbers: 0 etherStatsFragments: 3 ipaccTxConf: 0 ipaccRxConf: 0 ipaccRxStat: 0 ipaccRxStatSum: 0  

 

What could be the Problem? 

 

With best regards, 

 

Jan
0 Kudos
10 Replies
Altera_Forum
Honored Contributor II
132 Views

Hi, 

 

 

--- Quote Start ---  

 

 

i have a problem with my Ethernet on the DE2-115 Board using uClinux. 

When i set up "eth0": 

root:/> ifconfig eth0 192.168.14.92 up root:/> ifconfig eth0 eth0 Link encap:Ethernet HWaddr 00:11:22:33:44:55 inet addr:192.168.14.92 Bcast:192.168.14.255 Mask:255.255.255.0 UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:7 errors:7 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 Base address:0x2400  

There are 7 errors on RX-Line. 

 

When i do "ping": 

root:/> ping 192.168.14.14 PING 192.168.14.14 (192.168.14.14): 56 data bytes ^C --- 192.168.14.14 ping statistics --- 3 packets transmitted, 0 packets received, 100% packet loss root:/> ifconfig eth0 eth0 Link encap:Ethernet HWaddr 00:11:22:33:44:55 inet addr:192.168.14.92 Bcast:192.168.14.255 Mask:255.255.255.0 UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:43 errors:43 dropped:0 overruns:0 frame:0 TX packets:3 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 Base address:0x2400  

the Errors increase. 

 

Output of ethtool: 

root:/> ethtool eth0 Settings for eth0: Supported ports: Supported link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Half 1000baseT/Full Supports auto-negotiation: Yes Advertised link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Half 1000baseT/Full Advertised auto-negotiation: Yes Speed: 1000Mb/s Duplex: Full Port: MII PHYAD: 17 Transceiver: external Auto-negotiation: on Current message level: 0x00000000 (0) Link detected: yes  

 

root:/> ethtool -S eth0 NIC statistics: aFramesTransmittedOK: 3 aFramesReceivedOK: 0 aFramesCheckSequenceErrors: 3 aAlignmentErrors: 1 aOctetsTransmittedOK: 138 aOctetsReceivedOK: 0 aTxPAUSEMACCtrlFrames: 0 aRxPAUSEMACCtrlFrames: 0 ifInErrors: 47 ifOutErrors: 0 ifInUcastPkts: 0 ifInMulticastPkts: 0 ifInBroadcastPkts: 0 ifOutDiscards: 0 ifOutUcastPkts: 0 ifOutMulticastPkts: 0 ifOutBroadcastPkts: 3 etherStatsDropEvent: 0 etherStatsOctets: 120993 etherStatsPkts: 47 etherStatsUndersizePkts: 0 etherStatsOversizePkts: 0 etherStatsPkts64Octets: 0 etherStatsPkts65to127Octets: 40 etherStatsPkts128to255Octets: 3 etherStatsPkts256to511Octets: 0 etherStatsPkts512to1023Octets: 0 etherStatsPkts1024to1518Octets: 1 etherStatsPkts1519toXOctets: 0 etherStatsJabbers: 0 etherStatsFragments: 3 ipaccTxConf: 0 ipaccRxConf: 0 ipaccRxStat: 0 ipaccRxStatSum: 0  

 

What could be the Problem? 

 

 

--- Quote End ---  

 

 

Did you use a PLL to adjust the phase of Rx clock? 

 

Kazu
Altera_Forum
Honored Contributor II
132 Views

TO_BE_DONE

Altera_Forum
Honored Contributor II
132 Views

Hi, 

 

root:/> Oops: Exception in kernel mode, sig: 4 r1: 00000004 r2: cfc1e008 r3: 00000004 r4: 00000000 r5: cfc1ffa4 r6: 00000001 r7: 00000001 r8: 00000000 r9: c8734894 r10: 00000004 r11: 00000004 r12: 01000000 r13: 00000400 r14: 00000000 r15: d9274300 ra: c8000bbc fp: 00000000 sp: cfc1fe3c gp: 0000ca80 ea: c8002440 estatus: 00000001 Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000004  

 

Maybe sig:4 means that the CPU encounters an illegal instruction, so please get its objdump file like 

 

nios2-***-linux-gnu-objdump -d -S vmlinux > vmlinux.objdump  

 

and check whether the instruction located at 0xc8002440 is illegal or not. If the instruction is legal, I recommend you once to check the timing of SDRAM I/Os etc. 

 

Kazu
Altera_Forum
Honored Contributor II
132 Views

Thank you Kazu for helping me! :) 

 

The problem, why my TSE was not working, relays to wrong constrains. 

My design now is as followed: 

module uClinux( // Clock input CLOCK_50, // KEY input KEY, // Ethernet 1 output ENET1_GTX_CLK, output ENET1_MDC, inout ENET1_MDIO, output ENET1_RESET_N, input ENET1_RX_CLK, input ENET1_RX_DATA, input ENET1_RX_DV, output ENET1_TX_DATA, output ENET1_TX_EN, // SDRAM output DRAM_CLK, output DRAM_ADDR, output DRAM_BA, output DRAM_CAS_N, output DRAM_CKE, output DRAM_CS_N, inout DRAM_DQ, output DRAM_DQM, output DRAM_RAS_N, output DRAM_WE_N, // RS232 input UART_RXD, output UART_TXD ); wire sys_clk; wire enet_tx_clk_125, enet_tx_clk_25, enet_tx_clk_2p5, tx_clk; wire enet_gtx_clk_125, enet_gtx_clk_25, enet_gtx_clk_2p5; wire core_reset_n; wire mdc, mdio_in, mdio_oen, mdio_out; wire eth_mode, ena_10; assign mdio_in = ENET1_MDIO; assign ENET1_MDC = mdc; assign ENET1_MDIO = mdio_oen ? 1'bz : mdio_out; assign ENET1_RESET_N = core_reset_n; assign DRAM_CLK = sys_clk; assign ENET1_GTX_CLK = eth_mode ? enet_gtx_clk_125 : // GbE Mode = 125MHz clock ena_10 ? enet_gtx_clk_2p5 : // 10Mb Mode = 2.5MHz clock enet_gtx_clk_25; // 100Mb Mode = 25 MHz clock pll pll_inst( .areset (~KEY), .inclk0 (CLOCK_50), .c0 (sys_clk), .c1 (enet_tx_clk_125), .c2 (enet_tx_clk_25), .c3 (enet_tx_clk_2p5), .locked (core_reset_n) ); enet_pll_90 gtx_pll_inst( .areset (~KEY), .inclk0 (CLOCK_50), .c0 (enet_gtx_clk_125), .c1 (enet_gtx_clk_25), .c2 (enet_gtx_clk_2p5), .locked () ); assign tx_clk = eth_mode ? enet_tx_clk_125 : // GbE Mode = 125MHz clock ena_10 ? enet_tx_clk_2p5 : // 10Mb Mode = 2.5MHz clock enet_tx_clk_25; // 100Mb Mode = 25 MHz clock nios_system system_inst ( .reset_reset_n (core_reset_n), .clk_clk (sys_clk), .sdram_wire_addr (DRAM_ADDR), .sdram_wire_ba (DRAM_BA), .sdram_wire_cas_n (DRAM_CAS_N), .sdram_wire_cke (DRAM_CKE), .sdram_wire_cs_n (DRAM_CS_N), .sdram_wire_dq (DRAM_DQ), .sdram_wire_dqm (DRAM_DQM), .sdram_wire_ras_n (DRAM_RAS_N), .sdram_wire_we_n (DRAM_WE_N), .rs232_external_connection_rxd (UART_RXD), .rs232_external_connection_txd (UART_TXD), .tse_mac_conduit_connection_tx_clk (tx_clk), .tse_mac_conduit_connection_rx_clk (ENET1_RX_CLK), .tse_mac_conduit_connection_mdc (mdc), .tse_mac_conduit_connection_mdio_in (mdio_in), .tse_mac_conduit_connection_mdio_out (mdio_out), .tse_mac_conduit_connection_mdio_oen (mdio_oen), .tse_mac_conduit_connection_rgmii_in (ENET1_RX_DATA), .tse_mac_conduit_connection_rgmii_out (ENET1_TX_DATA), .tse_mac_conduit_connection_rx_control (ENET1_RX_DV), .tse_mac_conduit_connection_tx_control (ENET1_TX_EN), .tse_mac_conduit_connection_eth_mode (eth_mode), .tse_mac_conduit_connection_ena_10 (ena_10) ); endmodule
Altera_Forum
Honored Contributor II
132 Views

And my .sdc: 

create_clock -period 20 create_clock -name {enet_rx_clk_125} -period 8 create_clock -name {enet_rx_clk_25} -period 40 -add create_clock -name {enet_rx_clk_2_5} -period 400 -add create_clock -name {enet_rx_clk_125_virt} -period 8 -waveform { 2.000 6.000 } create_clock -name {enet_rx_clk_25_virt} -period 40 -waveform { 10.000 30.000 } create_clock -name {enet_rx_clk_2_5_virt} -period 400 -waveform { 100.000 300.000 } # Create Generated Clock create_generated_clock -source {pll_inst|altpll_component|auto_generated|pll1|inclk} -multiply_by 2 -duty_cycle 50.00 -name {sys_clk} {pll_inst|altpll_component|auto_generated|pll1|clk} create_generated_clock -source {pll_inst|altpll_component|auto_generated|pll1|inclk} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {enet_tx_clk_125} {pll_inst|altpll_component|auto_generated|pll1|clk} create_generated_clock -source {pll_inst|altpll_component|auto_generated|pll1|inclk} -divide_by 2 -multiply_by 1 -duty_cycle 50.00 -name {enet_tx_clk_25} {pll_inst|altpll_component|auto_generated|pll1|clk} create_generated_clock -source {pll_inst|altpll_component|auto_generated|pll1|inclk} -divide_by 20 -multiply_by 1 -duty_cycle 50.00 -name {enet_tx_clk_2p5} {pll_inst|altpll_component|auto_generated|pll1|clk} create_generated_clock -source {gtx_pll_inst|altpll_component|auto_generated|pll1|inclk} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -phase 90 -name {enet_gtx_clk_125} {gtx_pll_inst|altpll_component|auto_generated|pll1|clk} create_generated_clock -source {gtx_pll_inst|altpll_component|auto_generated|pll1|inclk} -divide_by 2 -multiply_by 1 -duty_cycle 50.00 -phase 90 -name {enet_gtx_clk_25} {gtx_pll_inst|altpll_component|auto_generated|pll1|clk} create_generated_clock -source {gtx_pll_inst|altpll_component|auto_generated|pll1|inclk} -divide_by 20 -multiply_by 1 -duty_cycle 50.00 -phase 90 -name {enet_gtx_clk_2p5} {gtx_pll_inst|altpll_component|auto_generated|pll1|clk} # Set Input Delay set_input_delay -clock enet_rx_clk_125_virt -max 2.5 ENET1_RX_DV}] -add_delay set_input_delay -clock enet_rx_clk_125_virt -max 2.5 ENET1_RX_DV}] -clock_fall -add_delay set_input_delay -clock enet_rx_clk_125_virt -min 1.5 ENET1_RX_DV}] -add_delay set_input_delay -clock enet_rx_clk_125_virt -min 1.5 ENET1_RX_DV}] -clock_fall -add_delay set_input_delay -clock enet_rx_clk_25_virt -max 2.5 ENET1_RX_DV}] -add_delay set_input_delay -clock enet_rx_clk_25_virt -max 2.5 ENET1_RX_DV}] -clock_fall -add_delay set_input_delay -clock enet_rx_clk_25_virt -min 1.5 ENET1_RX_DV}] -add_delay set_input_delay -clock enet_rx_clk_25_virt -min 1.5 ENET1_RX_DV}] -clock_fall -add_delay set_input_delay -clock enet_rx_clk_2_5_virt -max 2.5 ENET1_RX_DV}] -add_delay set_input_delay -clock enet_rx_clk_2_5_virt -max 2.5 ENET1_RX_DV}] -clock_fall -add_delay set_input_delay -clock enet_rx_clk_2_5_virt -min 1.5 ENET1_RX_DV}] -add_delay set_input_delay -clock enet_rx_clk_2_5_virt -min 1.5 ENET1_RX_DV}] -clock_fall -add_delay # Set Output Delay set_output_delay -clock enet_tx_clk_125 -min -0.5 ENET1_TX_EN}] -add_delay set_output_delay -clock enet_tx_clk_125 -max -clock_fall 0.5 ENET1_TX_EN}] -add_delay set_output_delay -clock enet_tx_clk_125 -max 0.5 ENET1_TX_EN}] -add_delay set_output_delay -clock enet_tx_clk_125 -min -clock_fall -0.5 ENET1_TX_EN}] -add_delay set_output_delay -clock enet_tx_clk_25 -min -0.5 ENET1_TX_EN}] -add_delay set_output_delay -clock enet_tx_clk_25 -max -clock_fall 0.5 ENET1_TX_EN}] -add_delay set_output_delay -clock enet_tx_clk_25 -max 0.5 ENET1_TX_EN}] -add_delay set_output_delay -clock enet_tx_clk_25 -min -clock_fall -0.5 ENET1_TX_EN}] -add_delay set_output_delay -clock enet_tx_clk_2p5 -min -0.5 ENET1_TX_EN}] -add_delay set_output_delay -clock enet_tx_clk_2p5 -max -clock_fall 0.5 ENET1_TX_EN}] -add_delay set_output_delay -clock enet_tx_clk_2p5 -max 0.5 ENET1_TX_EN}] -add_delay set_output_delay -clock enet_tx_clk_2p5 -min -clock_fall -0.5 ENET1_TX_EN}] -add_delay # Set Clock Groups set_clock_groups -exclusive -group -group -group -group -group -group -group -group -group -group # Set False Path set_false_path -from set_false_path -to set_false_path -setup -rise_from enet_tx_clk_125 -fall_to enet_gtx_clk_125 set_false_path -setup -fall_from enet_tx_clk_125 -rise_to enet_gtx_clk_125 set_false_path -hold -rise_from enet_tx_clk_125 -rise_to enet_gtx_clk_125 set_false_path -hold -fall_from enet_tx_clk_125 -fall_to enet_gtx_clk_125 set_false_path -setup -rise_from enet_tx_clk_25 -fall_to enet_gtx_clk_25 set_false_path -setup -fall_from enet_tx_clk_25 -rise_to enet_gtx_clk_25 set_false_path -hold -rise_from enet_tx_clk_25 -rise_to enet_gtx_clk_25 set_false_path -hold -fall_from enet_tx_clk_25 -fall_to enet_gtx_clk_25 set_false_path -setup -rise_from enet_tx_clk_2p5 -fall_to enet_gtx_clk_2p5 set_false_path -setup -fall_from enet_tx_clk_2p5 -rise_to enet_gtx_clk_2p5 set_false_path -hold -rise_from enet_tx_clk_2p5 -rise_to enet_gtx_clk_2p5 set_false_path -hold -fall_from enet_tx_clk_2p5 -fall_to enet_gtx_clk_2p5 set_false_path -fall_from enet_rx_clk_125_virt -rise_to enet_rx_clk_125 -setup set_false_path -rise_from enet_rx_clk_125_virt -fall_to enet_rx_clk_125 -setup set_false_path -rise_from enet_rx_clk_125_virt -rise_to enet_rx_clk_125 -hold set_false_path -fall_from enet_rx_clk_125_virt -fall_to enet_rx_clk_125 -hold set_false_path -fall_from enet_rx_clk_25_virt -rise_to enet_rx_clk_25 -setup set_false_path -rise_from enet_rx_clk_25_virt -fall_to enet_rx_clk_25 -setup set_false_path -rise_from enet_rx_clk_25_virt -rise_to enet_rx_clk_25 -hold set_false_path -fall_from enet_rx_clk_25_virt -fall_to enet_rx_clk_25 -hold set_false_path -fall_from enet_rx_clk_2_5_virt -rise_to enet_rx_clk_2_5 -setup set_false_path -rise_from enet_rx_clk_2_5_virt -fall_to enet_rx_clk_2_5 -setup set_false_path -rise_from enet_rx_clk_2_5_virt -rise_to enet_rx_clk_2_5 -hold set_false_path -fall_from enet_rx_clk_2_5_virt -fall_to enet_rx_clk_2_5 -hold # Set Multicycle Path set_multicycle_path -from enet_tx_clk_125 -to enet_gtx_clk_125 -setup -start 2 set_multicycle_path -from enet_tx_clk_25 -to enet_gtx_clk_25 -setup -start 2 set_multicycle_path -from enet_tx_clk_2p5 -to enet_gtx_clk_2p5 -setup -start 2 # Set Maximum Delay set_max_delay -from enet_gtx_clk_125 -to 20 set_max_delay -from enet_gtx_clk_25 -to 20 set_max_delay -from enet_gtx_clk_2p5 -to 20 # Set Minimum Delay set_min_delay -from enet_gtx_clk_125 -to 0 set_min_delay -from enet_gtx_clk_25 -to 0 set_min_delay -from enet_gtx_clk_2p5 -to 0
Altera_Forum
Honored Contributor II
132 Views

To RoyalOpino : 

Maybe you can try the tools modelsim and Eclipse IDE to test your TSE works well or not . 

 

kindly regards 

Altera_Forum
Honored Contributor II
132 Views

Hi, 

 

To Mr. RoyalOpino 

 

 

--- Quote Start ---  

 

The problem, why my TSE was not working, relays to wrong constrains. 

My design now is as followed: 

 

--- Quote End ---  

 

 

May I interpret that you succeeded using your TSE ? 

 

To Mr. fdsa 

 

 

--- Quote Start ---  

 

core dumped... 

 

with the same result 2: 

 

Code: 

 

r1: c026ec90 r2: c0354000 r3: c0354000 r4: c0354000 

r5: 00000001 r6: 00000000 r7: 00000000 r8: 00000000 

r9: 00000008 r10: 00000171 r11: c035aacc r12: c0356a3c 

r13: c0356a40 r14: ffffffe4 r15: c020d81c 

ra: c026f520 fp: deadbeef sp: c025ef9c gp: deadbeef 

ea: c026f614 estatus: 00000000 

Unaligned access from kernel mode, this might be a hardware 

problem, dump registers and restart the instruction 

BADADDR 0xdeadbf0f 

cause 7 

op-code 0xb800283a 

 

 

--- Quote End ---  

 

 

The core dumped contents are same for both 'nios2-terminal < linux.initramfs.srec' and 'nios2-download -g zImage' ? In my circumstances, 'nios2-download' which is using 'JTAG Debugger' will not work well. 

And it's better for us to make a new thread and discuss these things. 

 

Kazu
Altera_Forum
Honored Contributor II
132 Views

 

--- Quote Start ---  

Hi, 

 

To Mr. RoyalOpino 

 

 

 

May I interpret that you succeeded using your TSE ? 

 

 

--- Quote End ---  

 

 

Yes I did :) Thank you very much :cool:
Altera_Forum
Honored Contributor II
132 Views

sorry for reopening this thread. But it is not possible for me opening a new one and I have the same issue. 

 

I am working with Quartus V14.1 and running Linux Yocto/Angstrom 

 

Linux is booting and loading altera_tse driver. 

But it doesn't recognise the tse_interfaces. 

On boot up the following error message shows up: altera_tse c0010000.ethernet: resource s1 not defined. 

(c0010000 is the base address of the tse_interface) 

I didn't find any information about what to add to the xml files for generating the right dtb file. 

As much as possible I followed the instructions from: http://rocketboards.org/foswiki/projects/alterasoctriplespeedethernetdesignexample 

But the dtb generation is in quartus 14.1 other than in quartus 14.0 

 

Where do I get the information what to add in the xml files? 

Can you tell me, what to add? 

 

thanks in advance, 

 

Fabian
Altera_Forum
Honored Contributor II
132 Views

sorry for reopening this thread. 

 

I think I have a problem which was here solved, so I hope the right people will read it... 

 

I try to get tse working. 

Installed is Quartus V14.1 and I work with the cyclone V. 

I followed the instructions of rocketboards: http://rocketboards.org/foswiki/projects/alterasoctriplespeedethernetdesignexample 

 

My problem is the difference of the quartus versions. So I can't take the dtb of the example. I think my one has another look. 

My Linux which boots, is Yocto Angstrom kernel 3.10. 

at boot up it says: 

altera_tse c0010000.ethernet: resource s1 not defined 

altera_tse c0015000.ethernet: resource s1 not defined 

 

c0010000 / c0015000 are the base addresses of the tse-IPs. 

Where do I get the information, what to add to the xml files for dts/ dtb generation? 

I feel like searching the whole web, but nowhere I get answers... 

 

Thanks in advance, 

Fabian
Reply