Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12600 Discussions

user2 clock can be enabled in qsys system under soc. But not allowed to modify?

Altera_Forum
Honored Contributor II
1,338 Views

Hi All, 

 

I was designing the system in Cyclone V soc, and i am enable all 3 clock... but some how the clock user 2 can be enable, but ther e is not field i could change the frequency... how to change the frequency anyway? 

 

 

RB, 

supu
0 Kudos
6 Replies
Altera_Forum
Honored Contributor II
443 Views

I remember they do not provide a modification slot in the qsys system for the clock mode.... where.. you can modify this in the source code, go search for the key word CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT. where u can just change this from there.

0 Kudos
Altera_Forum
Honored Contributor II
443 Views

any way to make qsys to support the modification?

0 Kudos
Altera_Forum
Honored Contributor II
443 Views

no idea, i notice the 15.0 still not support for that area.... but at least just change the code directly and move on first....

0 Kudos
Altera_Forum
Honored Contributor II
443 Views

This is no big deal issue, as we can still modify in another way.

0 Kudos
Altera_Forum
Honored Contributor II
443 Views

Okay.. could you point to me where is this file located for changes?

0 Kudos
Altera_Forum
Honored Contributor II
443 Views

is in your project folder....

0 Kudos
Reply