Hello,I'm working on a custom pcb with a cyclone V GX. I'm having issues getting an output from the altera megafunction PLL, it is unresponsive. My test design has a nios II which successfully runs the hello world example without using any sort of PLL (just straight clock from the input pin), however when I implement a PLL prior to the clock input for the processor, the JTAG fails for the CPU. I have set the outputs of the PLL to pins and am receiving no signal when scoped. My thought is that it may be an input clock issue (PLL unable to lock) but the clock looks fine on a scope and the nios processor didn't seem to have a problem with it (prior to inserting the PLL). Running out of ideas on what to test, any thoughts? I appreciate any help. Thanks, Nick
Yes, I have. It is low showing low and that it is not locked. I just cant seem to figure out why it wouldn't lock if my clock line seems fine.Are there any other PLL debugging techniques I could try? Thanks again.
Are you generating phase shifted clock from PLL? If yes then provide phaseshift in ps instead of degree. I faced this issue with Altera PLL megafunction.Are you using SDRAM as a program memory for NIOS? If yes then there is chance after inserting PLL,SDRAM clock routing is changed and due to that SDRAM is not working. To test the hello world you can use ONCHIP Memory.