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Altera_Forum
Honored Contributor I
992 Views

why nios occupy much more M9K blocks than its on-chip memory size?

hi, everyone. 

i use max10 08SAE, it has 387.072 bits , 44 M9K 

i build a nios system, with 20480 bytes on chip memory (20480*8=163840 bits),  

after compile the project, the report shows the project use 33% of the total memory. 

but when i check the ram summary in fitter=>resource sention=>ram summary 

i find the nios use 42 M9K rams!, almost use all of the block ram on the chip! 

 

in the report, the on-chip memory use 32 M9Ks! but it size is only 163840 bits! 

the report shows the on-chip memory depth is 5120, width is 32bits 

 

 

i have following questions: 

1. why is cost so many M9Ks? is there any way to prevent this situation? 

 

 

2.how should i set the on-chip memory size, to use the rams on fpga more efficiently? 

 

 

 

btw: i up load the ram report
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4 Replies
Altera_Forum
Honored Contributor I
55 Views

Hi, 

 

The On-Chip Ram uses 32M9Ks as Row 46 shows, and as you could see eg in line 39, a 8x64 Fifo-instantiation needs 512 Bits out of one M9K. The rest of the M9K is no longer useable by other functionality, so one more M9K is unavailable. 

 

I hope this helps.
Altera_Forum
Honored Contributor I
55 Views

thanks for your reply. 

from the " test_ft245-RAM Summary.txt" file, i have seen which block occupy how many M9ks. 

but i do not understand why it cost so many? and how to use the M9K more efficiently? 

 

for example: 

1. The nios' On-Chip Ram uses 32M9Ks as " test_ft245-RAM Summary.txt" file Row 46 shows, but the On-Chip Ram size is 163840 bits, the depth is 5120 and the width is 32bit, it is in Single Port mode. 

the total size of 32M9Ks is 294,912bits , almost twice the size of the On-Chip Ram size. 

and i check the MAX 10 FPGA datasheet, each M9Ks can be set as a 256*36 single port ram, so 163840 bits should only occupy 20 M9Ks. 

 

2.as you see, a 8x64 Fifo-instantiation needs 512 Bits out of one M9K, but it occupy 1 M9K. 

so the rest memory of this M9K has been waste. to this design, this fifo size can be set to 9K without consume more rescoure.  

how to change the design, so the rescources can be used more efficiently? 

 

thanks!
Altera_Forum
Honored Contributor I
55 Views

i figure out these questions: 

1. 

in the digital binary system, the 5120*32bit occupy the same resourses as 9182*32bit. so in order to use the M9K more efficiently, i should change the On-Chip Ram size from 5120*32 to 4096*32. 

i test this method on my project, and i works. 

 

2. 

the "jtag_uart_0_scfifo_r" and the "jtag_uart_0_scfifo_w" only have 512 bits, but each of them occupy 1 M9k, so i enlarge the JTAG UART fifo buffer depth from 64 to 1152, so the system gets more JTAG UART fifo buffer depth without cost more M9ks.
Altera_Forum
Honored Contributor I
55 Views

You can try reduce your Nios I-Cache size. Currently, it is set to 32KB?

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