writing vhdl code in nios ii processor

[Altera_Forum]

Hello everyone. I am currently doing a project on cyclone iii fpga starter kit. In my project I made a counter that counts calue from 0 to 10. I want to first write these values in ssram by pressing a key and read them back in 4 LEDS by pressing another key.For this i made a Nios ii processor.My problem is I want to connect this vhdl file to the nios processor and i do not want to use c.I want to make interface like thing to write in ssram. I do not know for this I have to write data and addresses and read write enable on bus or not?? Plz anyone help me because I am stucked here from 3 days... :(

[Altera_Forum]

Hi, so you want a simple project. 

 I suppose you have a QSYS wich implements NiosII, SSRAM.... that you pick from an Altera demo. I suggest you to use one PIO (Parallel Input Output) to read your counter  an other PIO to "write" to the LEDs, a PIO to read your keys (if any).  What did you already make ?

[Altera_Forum]

Hi mmTsuchi, 

 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; --use ieee.std_logic_arith.all; use ieee.numeric_std.all; use IEEE.math_real.all;    entity countervhdl is   generic   (  DATA_WIDTH : natural := 2;  ADDR_WIDTH : natural := 5  );     port( clk : in std_logic;  --raddr : in natural range 0 to 2**ADDR_WIDTH - 1;  waddr : in natural range 0 to 2**ADDR_WIDTH - 1;  --data : in std_logic_vector((DATA_WIDTH-1) downto 0);  re : in std_logic := '1';  we : in std_logic := '1';  reset : in std_logic;  q : out std_logic_vector(3 downto 0)); end countervhdl;       architecture counting of countervhdl is  signal prescalar: integer range 0 to 50000000:=0;  signal pre: integer range 0 to 9;  signal count:integer range 0 to 9;   --signal   --subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);  type memory_t is array(2**ADDR_WIDTH-1 downto 0) of integer range 0 to 9;   -- Declare the RAM signal.   signal ram : memory_t;   -- Register to hold the address   --signal addr_reg : natural range 0 to 2**ADDR_WIDTH-1;   begin  process(clk,reset,pre)  --variable addr:integer range 0 to 2**ADDR_WIDTH-1;   variable ten:integer:=10; begin    if (clk = '1' and clk'event) then  if (prescalar<50000000) then  prescalar<=prescalar+1;  else prescalar<=0;  end if;  if (prescalar=0) then  --for addr in 0 to 9 loop  if (reset='1') then   if(we = '0') then  if pre<10 then  pre<=pre +1 ;   --elsif pre>10 then   -- pre<=0;  end if;  ram(waddr) <= pre;  --address<=addr;  end if;  if re='0' then   count<=ram(waddr);  q<=std_logic_vector(to_unsigned(count,4));--ram(addr);  end if;  end if;    end if;  end if;         end process;   end counting;   This is my code and i want to apply this in nios system made from qsys.I used sysid,nios processor, tristate bus, ext ssram clk, onchip memory jtag_uaert,pios for led and keys. Now my problem is how to connect these read, write, output from counter in the nios processor file that is generated from qsys. In the tutorials it says i can use only eclipse ide for this counter but anyhow i want to use vhdl code. ANd I get error when i generate vhdl file in qsys but it works with verilog.  Please help me.  Thanks

[Altera_Forum]

Hi, you can post your code within [ code] balises 

(just a detail : std_logic_unsigned is NOT an IEEE package, but you can use it)  Your code is .... good for Halloween :-)  for the process, you want a synchronous process so write   process(reset, clk) -- nothing else -- variables if any begin if reset = '1' then -- asynchronous variables and signals initializations here elsif rising_edge(clk) then ... end if; end process;   You should name "re_n" and "we_n" since they are active low.  You inferred a RAM... it is just an internal RAM to your counter, that will be difficult to read from QSYS What's happen  You inferred unwanted(?) delay : ram(waddr) ----> count ----> q. So you q is assigned after 2 clocks. All is quite confused.  ------------------ I suggest(only suggest) you to write a simple counter like this process(reset, clk) -- nothing else begin if reset = '1' then count <= 0; -- if count is integer with range 0 to 9 elsif rising_edge(clk) then if count < 9 then count <= count +1; else count <= 0; end if; end if; end process;   and then connect the "count" signal to a PIO for QSYS.  In software, just read the PIO : IORD_ALTERA_AVALON_PIO_DATA(PIO_COUNTER);

[Altera_Forum]

Hey thanks for rply. It was complete chaotisch. cant I give command to the processor for writing in address of ssram and then read counted value from ssram by using vhdl?? 

the software you mean the software from eclipse IDE i.e., C or?? Actually i want to handle all these things from the vhdl and then from keys from my board??  My main confusion is that i can write these counted value in ssram from vhdl or not??   thanks and sorry for my stupid code:)

[Altera_Forum]

Can u please give me some link to tutorial for writing and reading ssram using vhdl where I can apply my counter values? i am so much confused in these stuffs? 

 Thanks

[Altera_Forum]

By software, I mean software for NIOS II so C langage, yes. 

 Do you mean that your SSRAM will be shared by the NIOS II and your counter ?! In this case you (or Quartus) have to deal with arbitration : 2 components want to access 1 ressource. It becomes complicated, but possible.  Read and writing to an inferred RAM, you already do this in your VHDL code : "ram(waddr) <= pre;" to write to SSRAM,  "count<=ram(waddr);" to read from SSRAM but be aware that the Quartus fitter will infer a RAM with the ressources available (4k RAM block, or simply registers) and read this RAM from QSYS becomes tedious. I think it is a bad way of design. Not simple for a beginner.  what is your goal more precisely ? what is the wanted behaviour of your board ? your 1st post is not detailed enough.  You are afraid in writing in C like us with the monsters. If so then forget NIOS II :-)